Abstract: The present invention is directed to easily change design of RTL circuit data according to design specifications such as power consumption and operation frequency. RTL circuit data of a semiconductor integrated circuit includes a first description expressing a specific module or specific circuit element and a second description with which at least a part of the first description is replaced, thereby adding a new function to a specific module or circuit element. When a computer performs logic synthesis on the RTL circuit data, either logic synthesis is performed on the first description as it is, or a part of the first description is replaced with the second description and the logic synthesis is performed on the resultant is determined on the basis of selection information.

Abstract: A technique for generating an appropriate clock is provided. A clock generation circuit generates a logic-circuit clock on the basis of a reference clock and outputs the logic-circuit clock to a logic circuit. The clock generation circuit and the logic circuit are both supplied with power from a power supplier. According to a control signal from a power controller, the power supplier changes a power voltage value provided to the clock generation circuit and the logic circuit. The control signal is generated by the power controller on the basis of a counter value from the clock generation circuit. The counter value is obtained from a digital counter which determines the delay speeds of delay elements in a multiplier circuit in the clock generation circuit.

Abstract: A microcomputer comprises a serial interface for receiving a debugging program applied thereto from a debugging tool, a register for holding an instruction code included with the debugging program, which is applied to the microcomputer via the serial interface, and a central processing unit or CPU for executing the instruction code held by the first register to debug the microcomputer. The microcomputer can further comprise a buffer for holding one or more instruction codes supplied thereto from the register. The CPU can execute each of the plurality of instruction codes held by the buffer. Preferably, the serial interface is a JTAT (Joint Test Action Group) interface.

Abstract: A microcomputer of the present invention permits a direct control of a rewrite operation on an internal flash-memory to enhance the efficiency of a debugging operation. The microcomputer has a first storage means that stores a program for rewriting data into an internal flash memory, a second storage means that stores internal flash information about the internal flash memory, an interface that makes a connection to a debugging tool, and a CPU. The CPU allows reading of the internal flash information by the debugging tool through the interface, receiving of write data based on the internal flash information from the debugging tool through the interface, and rewriting of the write data as new contents into the internal flash memory in accordance with the program for rewriting data into the internal flash memory.