Patents by Inventor Fumitaka Kai

Fumitaka Kai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6162730
    Abstract: A method for efficiently fabricating semiconductor wafers of good planarization without utilizing chemical solutions of high etching rate is disclosed. The method slices a single-crystal ingot into slices of wafers. The edge of each wafer is chamfered. A lapping or grinding step is carried out to planarize the chamfered wafer. Both side surfaces of the wafer are then polished. Next, the wafer surface is mirror polished. Finally, the wafer is cleaned.
    Type: Grant
    Filed: February 12, 1999
    Date of Patent: December 19, 2000
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Fumitaka Kai, Masahiko Maeda, Jun-ichi Yamashita, Toshiharu Yubitani, Hirofumi Hajime, Takamitsu Harada
  • Patent number: 6043156
    Abstract: It is an object of the present invention to provide a method for efficiently making semiconductor wafers that prevents the production of metal pollution. It is another object of the present invention to provide a method where the back side of the wafer does not influence the front side, thereof, and where the front and back sides of the wafer can be distinguished are polishing.This invention provides a method for efficiently making semiconductor wafers having uniform thickness where the thickness of the back side does not influence the front side and where the front side of the wafer is capable of being distinguished from the back side. A semiconductor ingot is sliced to obtain wafers. The sliced surfaces of the wafers are flattened. The flattened wafer is etched in alkaline etching solution.
    Type: Grant
    Filed: October 29, 1997
    Date of Patent: March 28, 2000
    Assignee: Komatsu Electric Metals Co., Ltd.
    Inventors: Fumitaka Kai, Masahiko Maeda, Kenji Kawate
  • Patent number: 5963821
    Abstract: This invention provides a method for efficiently making semiconductor wafers having uniform thickness where the thickness of the back side does not influence the front side and where the front side of the wafer is capable of being distinguished from the back side. A semiconductor ingot is sliced to obtain wafers. The sliced surfaces of the wafers are flattened. The flattened wafer is etched in alkaline etching solution. Both the front and back sides of the etched wafer are polished using a double sided polishing apparatus so that the front side is a mirror surface and an unevenness remains on the back side to distinguish the front and back sides, thereof. The polished wafer is cleaned.
    Type: Grant
    Filed: October 29, 1997
    Date of Patent: October 5, 1999
    Assignee: Komatsu Electronic Metal Co., Ltd.
    Inventors: Fumitaka Kai, Masahiko Maeda, Kenji Kawate
  • Patent number: 5899731
    Abstract: A method of fabricating a semiconductor wafers, which can prevent metal contamination when alkali etching is used. A semiconductor ingot is cut into wafers. The peripheral portion of the sliced wafers is chamfered. The chamfered wafers are then planarized by lapping. The planarized wafers are alkali etched. The alkali etched wafers are subjected to acid washing by using diluted mixed acid solution. The surface of the acid-washed wafers are then polished. The polished wafers are washed again.
    Type: Grant
    Filed: September 10, 1997
    Date of Patent: May 4, 1999
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Fumitaka Kai, Masahiko Maeda, Kenji Kawate
  • Patent number: 5899743
    Abstract: A method for efficiently fabricating semiconductor wafers of good planarization without utilizing chemical solutions of high etching rate is disclosed. The method slices a single-crystal ingot into slices of wafers. The edge of each wafer is chamfered. A lapping step is carried out to planarize the chamfered wafer. Both side surfaces of the wafer are then polished. Next, the wafer surface is mirror polished. Finally, the wafer is cleaned.
    Type: Grant
    Filed: August 29, 1996
    Date of Patent: May 4, 1999
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Fumitaka Kai, Masahiko Maeda, Jun-ichi Yamashita, Toshiharu Yubitani, Hirofumi Hajime, Takamitsu Harada
  • Patent number: 5747364
    Abstract: A method of making semiconductor wafers can prevent processing strain on peripheral portions of wafers caused by non-wax polishing using a template. This involves mirror chamfering or etching the peripheral portions of the wafers after the non-wax polishing step.
    Type: Grant
    Filed: March 26, 1997
    Date of Patent: May 5, 1998
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Nobuyuki Akiyama, Fumitaka Kai, Masahiko Maeda, Hirofumi Hajime, Naoki Yamada