Patents by Inventor Fumito IMURA

Fumito IMURA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220341053
    Abstract: The plating machine 1 comprises a plurality of treatment units 14 and a conveying means 13 that conveys a wafer W to the plurality of treatment units 14, wherein the conveying means 13 includes an arm 31 that is provided, on one end side, with a plating tool 32 that holds the wafer W, and an arm rotation drive unit 33 that rotates the arm 31 around another end side of the arm 31, and the plurality of treatment units 14 is arranged at predetermined intervals on a rotation trajectory of the plating tool 32.
    Type: Application
    Filed: April 12, 2022
    Publication date: October 27, 2022
    Applicant: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Shiro HARA, Fumito IMURA, Sommawan KHUMPUANG, Yuuki ISHIDA, Toshihiro KIKUNO, Takafumi YOSHINAGA, Kayo KAMASAKI, Mitsuhiko FUKUYAMA, Tetuya MORIZONO
  • Patent number: 11056410
    Abstract: A method of manufacturing a semiconductor package and a semiconductor package in which positional alignment between a wafer and a substrate until the wafer is mounted and packaged on the substrate is achieved accurately. A wafer is mounted on a package substrate by using first alignment marks and D-cuts as benchmarks, and then a mold resin layer is formed on the wafer in a state in which the first alignment mark is exposed. A part of the mold resin layer is removed by using the D-cuts exposed from the mold resin layer as benchmarks, so that the first alignment marks can be visually recognized. A second alignment marks are formed on the mold resin layer by using the first alignment marks as benchmarks. A Cu redistribution layer to be conducted to a pad portion is formed on a mold resin layer by using the second alignment marks as benchmarks.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: July 6, 2021
    Assignee: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Shiro Hara, Sommawan Khumpuang, Fumito Imura
  • Publication number: 20200266119
    Abstract: A method of manufacturing a semiconductor package and a semiconductor package in which positional alignment between a wafer and a substrate until the wafer is mounted and packaged on the substrate is achieved accurately. A wafer is mounted on a package substrate by using first alignment marks and D-cuts as benchmarks, and then a mold resin layer is formed on the wafer in a state in which the first alignment mark is exposed. A part of the mold resin layer is removed by using the D-cuts exposed from the mold resin layer as benchmarks, so that the first alignment marks can be visually recognized. A second alignment marks are formed on the mold resin layer by using the first alignment marks as benchmarks. A Cu redistribution layer to be conducted to a pad portion is formed on a mold resin layer by using the second alignment marks as benchmarks.
    Type: Application
    Filed: March 28, 2018
    Publication date: August 20, 2020
    Applicant: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Shiro HARA, Sommawan KHUMPUANG, Fumito IMURA
  • Patent number: 10304675
    Abstract: A semiconductor manufacturing system has a series of steps, from manufacturing of a semiconductor on a wafer until packaging, that can be easily linked. A semiconductor chip manufacturing device manufactures a semiconductor chip, and a semiconductor packaging device packages the semiconductor chip by attaching the semiconductor chip to a package substrate which is larger than the wafer. The semiconductor chip manufacturing device includes a PLAD system for loading the wafer into and out of the semiconductor chip manufacturing device through a shuttle which is capable of housing the wafer. The semiconductor packaging device includes a PLAD system capable of loading the package substrate into and out of the semiconductor packaging device through a shuttle which is capable of housing the package substrate. The shuttles have container bodies of a same shape.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: May 28, 2019
    Assignee: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Michihiro Inoue, Shiro Hara, Fumito Imura, Arami Saruwatari, Sommawan Khumpuang
  • Patent number: 10163819
    Abstract: A method for manufacturing a surface-mount type package whose face parallel with the semiconductor chip surface has a circular cross-section, is characterized by including at least the following steps in this order: a first step in which a semiconductor chip is bonded onto a circular support substrate; a second step in which the semiconductor chip is sealed with resin; a third step in which the resin covering the pads of the semiconductor chip is removed; a fourth step in which a rewiring layer is formed; and a fifth step in which bumps are formed. The method can provide a surface-mount type package for semiconductor chips which is resistant to failures caused by thermal stress.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: December 25, 2018
    Assignee: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Shiro Hara, Sommawan Khumpuang, Fumito Imura, Michihiro Inoue, Arami Saruwatari
  • Patent number: 10163674
    Abstract: An object of the present invention is to provide a circular support substrate that allows for positioning based solely on its outer periphery shape. As a means for solving the problems, a circular support substrate is provided that has at least three chords along its circumference, wherein the chords are provided at positions where they do not run linearly symmetrical to the straight line passing through the center axis of the circular support substrate.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: December 25, 2018
    Assignee: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Shiro Hara, Sommawan Khumpuang, Fumito Imura, Michihiro Inoue, Arami Saruwatari
  • Publication number: 20180025994
    Abstract: An object of the present invention is to provide a surface-mount type package for semiconductor chips which is resistant to failures caused by thermal stress. As a means for achieving the object, a method for manufacturing a surface-mount type package whose face parallel with the semiconductor chip surface has a circular cross-section, is provided, wherein such method is characterized in that it comprises at least the following steps in this order. A first step in which a semiconductor chip is bonded onto a circular support substrate. A second step in which the semiconductor chip is sealed with resin. A third step in which the resin covering the pads of the semiconductor chip is removed. A fourth step in which a rewiring layer is formed. A fifth step in which bumps are formed.
    Type: Application
    Filed: November 24, 2015
    Publication date: January 25, 2018
    Inventors: Shiro HARA, Sommawan KHUMPUANG, Fumito IMURA, Michihiro INOUE, Arami SARUWATARI
  • Publication number: 20170352570
    Abstract: An object of the present invention is to provide a circular support substrate that allows for positioning based solely on its outer periphery shape. As a means for solving the problems, a circular support substrate is provided that has at least three chords along its circumference, wherein the chords are provided at positions where they do not run linearly symmetrical to the straight line passing through the center axis of the circular support substrate.
    Type: Application
    Filed: November 24, 2015
    Publication date: December 7, 2017
    Applicant: National Institute of Advanced Industrial Science and Technology
    Inventors: Shiro HARA, Sommawan KHUMPUANG, Fumito IMURA, Michihiro INOUE, Arami SARUWATARI
  • Publication number: 20170330741
    Abstract: A semiconductor manufacturing system has a series of steps, from manufacturing of a semiconductor on a wafer until packaging, that can be easily linked. A semiconductor chip manufacturing device manufactures a semiconductor chip, and a semiconductor packaging device packages the semiconductor chip by attaching the semiconductor chip to a package substrate which is larger than the wafer. The semiconductor chip manufacturing device includes a PLAD system for loading the wafer into and out of the semiconductor chip manufacturing device through a shuttle which is capable of housing the wafer. The semiconductor packaging device includes a PLAD system capable of loading the package substrate into and out of the semiconductor packaging device through a shuttle which is capable of housing the package substrate. The shuttles have container bodies of a same shape.
    Type: Application
    Filed: November 16, 2015
    Publication date: November 16, 2017
    Applicant: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Michihiro INOUE, Shiro HARA, Fumito IMURA, Arami SARUWATARI, Sommawan KHUMPUANG