Patents by Inventor Fumito Itoh

Fumito Itoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230182701
    Abstract: A control device for a vehicle configured to travel in a one-pedal mode in which driving and braking are controlled in response to operations on only an accelerator pedal is configured to control a braking force of the vehicle by using deceleration maps in which decelerations in a plurality of traveling directions are set for any points based on traveling history data, and calculate, during traveling in the one-pedal mode, a deceleration level based on deceleration information associated with a current traveling direction and a current position of the vehicle among pieces of deceleration information included in the deceleration maps.
    Type: Application
    Filed: October 13, 2022
    Publication date: June 15, 2023
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Fumito ITOH, Yusuke SUZUKI, Kosuke YAMAMOTO
  • Publication number: 20200254983
    Abstract: A brake force control system configured to allow a driver to control brake force finely only by operating an accelerator pedal, and to decelerate a vehicle to a target speed only by operating the accelerator pedal. The control system calculates a target deceleration to travel through a target site at a target speed in accordance with a decelerating factor. If a reference deceleration generated by returning the accelerator pedal to an initial position is equal to or less than the target deceleration, the control system increases the reference deceleration.
    Type: Application
    Filed: January 30, 2020
    Publication date: August 13, 2020
    Applicant: Toyota Jidosha Kabushiki Kaisha
    Inventors: Yusuke SUZUKI, Masaki OKAMURA, Junichi MURASE, Fumito ITOH
  • Patent number: 7538416
    Abstract: A resin molded type semiconductor device has: a semiconductor chip (12) which is mounted on a die pad portion (11) of a lead frame (9); thin metal wires (14) which connect terminals of the semiconductor chip (12) to inner lead portions (13) of the lead frame (9); and a sealing resin (15), and the lead frame (9) is subjected to an upsetting process so that a supporting portion (11) is located at a position higher than the inner lead portions (13). Since the sealing resin of a thickness corresponding to the step difference of the upsetting exists below the supporting portion, the adhesiveness between the lead frame and the sealing resin can be improved, and high reliability and thinning are realized.
    Type: Grant
    Filed: November 19, 2004
    Date of Patent: May 26, 2009
    Assignee: Panasonic Corporation
    Inventors: Masanori Minamio, Satoru Konishi, Yoshihiko Morishita, Yuichiro Yamada, Fumito Itoh
  • Patent number: 6900524
    Abstract: A resin molded type semiconductor device has: a semiconductor chip (12) which is mounted on a die pad portion (11) of a lead frame (9); thin metal wires (14) which connect terminals of the semiconductor chip (12) to inner lead portions (13) of the lead frame (9); and a sealing resin (15), and the lead frame (9) is subjected to an upsetting process so that a supporting portion (11) is located at a position higher than the inner lead portions (13). Since the sealing resin of a thickness corresponding to the step difference of the upsetting exists below the supporting portion, the adhesiveness between the lead frame and the sealing resin can be improved, and high reliability and thinning are realized.
    Type: Grant
    Filed: June 8, 1998
    Date of Patent: May 31, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masanori Minamio, Satoru Konishi, Yoshihiko Morishita, Yuichiro Yamada, Fumito Itoh
  • Publication number: 20050087890
    Abstract: A resin molded type semiconductor device has: a semiconductor chip (12) which is mounted on a die pad portion (11) of a lead frame (9); thin metal wires (14) which connect terminals of the semiconductor chip (12) to inner lead portions (13) of the lead frame (9); and a sealing resin (15), and the lead frame (9) is subjected to an upsetting process so that a supporting portion (11) is located at a position higher than the inner lead portions (13). Since the sealing resin of a thickness corresponding to the step difference of the upsetting exists below the supporting portion, the adhesiveness between the lead frame and the sealing resin can be improved, and high reliability and thinning are realized.
    Type: Application
    Filed: November 19, 2004
    Publication date: April 28, 2005
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Masanori Minamio, Satoru Konishi, Yoshihiko Morishita, Yuichiro Yamada, Fumito Itoh
  • Patent number: 6861735
    Abstract: A resin molded type semiconductor device has: a semiconductor chip (12) which is mounted on a die pad portion (11) of a lead frame (9); thin metal wires (14) which connect terminals of the semiconductor chip (12) to inner lead portions (13) of the lead frame (9); and a sealing resin (15), and the lead frame (9) is subjected to an upsetting process so that a supporting portion (11) is located at a position higher than the inner lead portions (13). Since the sealing resin of a thickness corresponding to the step difference of the upsetting exists below the supporting portion, the adhesiveness between the lead frame and the sealing resin can be improved, and high reliability and thinning are realized.
    Type: Grant
    Filed: December 31, 2003
    Date of Patent: March 1, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masanori Minamio, Satoru Konishi, Yoshihiko Morishita, Yuichiro Yamada, Fumito Itoh
  • Publication number: 20040150078
    Abstract: A resin molded type semiconductor device has: a semiconductor chip (12) which is mounted on a die pad portion (11) of a lead frame (9); thin metal wires (14) which connect terminals of the semiconductor chip (12) to inner lead portions (13) of the lead frame (9); and a sealing resin (15), and the lead frame (9) is subjected to an upsetting process so that a supporting portion (11) is located at a position higher than the inner lead portions (13). Since the sealing resin of a thickness corresponding to the step difference of the upsetting exists below the supporting portion, the adhesiveness between the lead frame and the sealing resin can be improved, and high reliability and thinning are realized.
    Type: Application
    Filed: December 31, 2003
    Publication date: August 5, 2004
    Inventors: Masanori Minamio, Satoru Konishi, Yoshihiko Morishita, Yuichiro Yamada, Fumito Itoh
  • Patent number: 6130115
    Abstract: A plastic encapsulated semiconductor device comprises a die pad, die pad support pins suspending the die pad, a semiconductor chip mounted on the die pad, thin metal wires for connecting the electrode of the semiconductor chip to leads, and a sealing resin sealing the foregoing components, while the respective bottom faces of the leads forming terminal portions are exposed. An upset process is performed with respect to the die pad support pins of a lead frame to form stepped portions such that the die pad is positioned higher in level than the leads. Since the lower portion of the sealing resin also underlies the die pad, enhanced adhesion is achieved between the die pad and the sealing rein, resulting in higher reliability. With the die pad positioned higher in level than the leads, there is no possibility of interference between the leads and the semiconductor chip even when the size of the semiconductor chip is freely changed.
    Type: Grant
    Filed: June 15, 1999
    Date of Patent: October 10, 2000
    Assignee: Matsushita Electronics Corporation
    Inventors: Ichiro Okumura, Masanori Minamio, Akio Kuito, Takeshi Morikawa, Toshiyuki Fukuda, Fumito Itoh
  • Patent number: 5942794
    Abstract: A plastic encapsulated semiconductor device comprises a die pad, die pad support pins suspending the die pad, a semiconductor chip mounted on the die pad, thin metal wires for connecting the electrode of the semiconductor chip to leads, and a sealing resin sealing the foregoing components, while the respective bottom faces of the leads forming terminal portions are exposed. An upset process is performed with respect to the die pad support pins of a lead frame to form stepped portions such that the die pad is positioned higher in level than the leads. Since the lower portion of the sealing resin also underlies the die pad, enhanced adhesion is achieved between the die pad and the sealing rein, resulting in higher reliability. With the die pad positioned higher in level than the leads, there is no possibility of interference between the leads and the semiconductor chip even when the size of the semiconductor chip is freely changed.
    Type: Grant
    Filed: October 21, 1997
    Date of Patent: August 24, 1999
    Assignee: Matsushita Electronics Corporation
    Inventors: Ichiro Okumura, Masanori Minamio, Akio Kuito, Takeshi Morikawa, Toshiyuki Fukuda, Fumito Itoh