Patents by Inventor Fumito Itoh
Fumito Itoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230182701Abstract: A control device for a vehicle configured to travel in a one-pedal mode in which driving and braking are controlled in response to operations on only an accelerator pedal is configured to control a braking force of the vehicle by using deceleration maps in which decelerations in a plurality of traveling directions are set for any points based on traveling history data, and calculate, during traveling in the one-pedal mode, a deceleration level based on deceleration information associated with a current traveling direction and a current position of the vehicle among pieces of deceleration information included in the deceleration maps.Type: ApplicationFiled: October 13, 2022Publication date: June 15, 2023Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Fumito ITOH, Yusuke SUZUKI, Kosuke YAMAMOTO
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Publication number: 20200254983Abstract: A brake force control system configured to allow a driver to control brake force finely only by operating an accelerator pedal, and to decelerate a vehicle to a target speed only by operating the accelerator pedal. The control system calculates a target deceleration to travel through a target site at a target speed in accordance with a decelerating factor. If a reference deceleration generated by returning the accelerator pedal to an initial position is equal to or less than the target deceleration, the control system increases the reference deceleration.Type: ApplicationFiled: January 30, 2020Publication date: August 13, 2020Applicant: Toyota Jidosha Kabushiki KaishaInventors: Yusuke SUZUKI, Masaki OKAMURA, Junichi MURASE, Fumito ITOH
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Patent number: 7538416Abstract: A resin molded type semiconductor device has: a semiconductor chip (12) which is mounted on a die pad portion (11) of a lead frame (9); thin metal wires (14) which connect terminals of the semiconductor chip (12) to inner lead portions (13) of the lead frame (9); and a sealing resin (15), and the lead frame (9) is subjected to an upsetting process so that a supporting portion (11) is located at a position higher than the inner lead portions (13). Since the sealing resin of a thickness corresponding to the step difference of the upsetting exists below the supporting portion, the adhesiveness between the lead frame and the sealing resin can be improved, and high reliability and thinning are realized.Type: GrantFiled: November 19, 2004Date of Patent: May 26, 2009Assignee: Panasonic CorporationInventors: Masanori Minamio, Satoru Konishi, Yoshihiko Morishita, Yuichiro Yamada, Fumito Itoh
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Patent number: 6900524Abstract: A resin molded type semiconductor device has: a semiconductor chip (12) which is mounted on a die pad portion (11) of a lead frame (9); thin metal wires (14) which connect terminals of the semiconductor chip (12) to inner lead portions (13) of the lead frame (9); and a sealing resin (15), and the lead frame (9) is subjected to an upsetting process so that a supporting portion (11) is located at a position higher than the inner lead portions (13). Since the sealing resin of a thickness corresponding to the step difference of the upsetting exists below the supporting portion, the adhesiveness between the lead frame and the sealing resin can be improved, and high reliability and thinning are realized.Type: GrantFiled: June 8, 1998Date of Patent: May 31, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Masanori Minamio, Satoru Konishi, Yoshihiko Morishita, Yuichiro Yamada, Fumito Itoh
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Publication number: 20050087890Abstract: A resin molded type semiconductor device has: a semiconductor chip (12) which is mounted on a die pad portion (11) of a lead frame (9); thin metal wires (14) which connect terminals of the semiconductor chip (12) to inner lead portions (13) of the lead frame (9); and a sealing resin (15), and the lead frame (9) is subjected to an upsetting process so that a supporting portion (11) is located at a position higher than the inner lead portions (13). Since the sealing resin of a thickness corresponding to the step difference of the upsetting exists below the supporting portion, the adhesiveness between the lead frame and the sealing resin can be improved, and high reliability and thinning are realized.Type: ApplicationFiled: November 19, 2004Publication date: April 28, 2005Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Masanori Minamio, Satoru Konishi, Yoshihiko Morishita, Yuichiro Yamada, Fumito Itoh
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Patent number: 6861735Abstract: A resin molded type semiconductor device has: a semiconductor chip (12) which is mounted on a die pad portion (11) of a lead frame (9); thin metal wires (14) which connect terminals of the semiconductor chip (12) to inner lead portions (13) of the lead frame (9); and a sealing resin (15), and the lead frame (9) is subjected to an upsetting process so that a supporting portion (11) is located at a position higher than the inner lead portions (13). Since the sealing resin of a thickness corresponding to the step difference of the upsetting exists below the supporting portion, the adhesiveness between the lead frame and the sealing resin can be improved, and high reliability and thinning are realized.Type: GrantFiled: December 31, 2003Date of Patent: March 1, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Masanori Minamio, Satoru Konishi, Yoshihiko Morishita, Yuichiro Yamada, Fumito Itoh
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Publication number: 20040150078Abstract: A resin molded type semiconductor device has: a semiconductor chip (12) which is mounted on a die pad portion (11) of a lead frame (9); thin metal wires (14) which connect terminals of the semiconductor chip (12) to inner lead portions (13) of the lead frame (9); and a sealing resin (15), and the lead frame (9) is subjected to an upsetting process so that a supporting portion (11) is located at a position higher than the inner lead portions (13). Since the sealing resin of a thickness corresponding to the step difference of the upsetting exists below the supporting portion, the adhesiveness between the lead frame and the sealing resin can be improved, and high reliability and thinning are realized.Type: ApplicationFiled: December 31, 2003Publication date: August 5, 2004Inventors: Masanori Minamio, Satoru Konishi, Yoshihiko Morishita, Yuichiro Yamada, Fumito Itoh
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Patent number: 6130115Abstract: A plastic encapsulated semiconductor device comprises a die pad, die pad support pins suspending the die pad, a semiconductor chip mounted on the die pad, thin metal wires for connecting the electrode of the semiconductor chip to leads, and a sealing resin sealing the foregoing components, while the respective bottom faces of the leads forming terminal portions are exposed. An upset process is performed with respect to the die pad support pins of a lead frame to form stepped portions such that the die pad is positioned higher in level than the leads. Since the lower portion of the sealing resin also underlies the die pad, enhanced adhesion is achieved between the die pad and the sealing rein, resulting in higher reliability. With the die pad positioned higher in level than the leads, there is no possibility of interference between the leads and the semiconductor chip even when the size of the semiconductor chip is freely changed.Type: GrantFiled: June 15, 1999Date of Patent: October 10, 2000Assignee: Matsushita Electronics CorporationInventors: Ichiro Okumura, Masanori Minamio, Akio Kuito, Takeshi Morikawa, Toshiyuki Fukuda, Fumito Itoh
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Patent number: 5942794Abstract: A plastic encapsulated semiconductor device comprises a die pad, die pad support pins suspending the die pad, a semiconductor chip mounted on the die pad, thin metal wires for connecting the electrode of the semiconductor chip to leads, and a sealing resin sealing the foregoing components, while the respective bottom faces of the leads forming terminal portions are exposed. An upset process is performed with respect to the die pad support pins of a lead frame to form stepped portions such that the die pad is positioned higher in level than the leads. Since the lower portion of the sealing resin also underlies the die pad, enhanced adhesion is achieved between the die pad and the sealing rein, resulting in higher reliability. With the die pad positioned higher in level than the leads, there is no possibility of interference between the leads and the semiconductor chip even when the size of the semiconductor chip is freely changed.Type: GrantFiled: October 21, 1997Date of Patent: August 24, 1999Assignee: Matsushita Electronics CorporationInventors: Ichiro Okumura, Masanori Minamio, Akio Kuito, Takeshi Morikawa, Toshiyuki Fukuda, Fumito Itoh