Patents by Inventor Fumitoshi Ikegaya

Fumitoshi Ikegaya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10738389
    Abstract: A semiconductor manufacturing apparatus according to an embodiment comprises a container contains a mixed solution that includes a processing solution for plating processing of a substrate and an additive and being capable of draining a part of the mixed solution when a first condition is satisfied. A first supplier supplies the processing solution to the container. A second supplier supplies the additive to the container when the first condition is satisfied and drainage of a part of the mixed solution is finished.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: August 11, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Takashi Izumi, Fumitoshi Ikegaya
  • Patent number: 10483126
    Abstract: A semiconductor manufacturing apparatus according to the present embodiment has a mount unit capable of mounting a substrate. A first supplier supplies a chemical solution onto the substrate. A first protection plate is provided along an outer circumference of the substrate, to receive the chemical solution splashing from the substrate. A second supplier is provided above the first protection plate, to supply a cleaning solution to an inner surface of the first protection plate.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: November 19, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takashi Izumi, Fumitoshi Ikegaya
  • Publication number: 20180226268
    Abstract: A semiconductor manufacturing apparatus according to the present embodiment has a mount unit capable of mounting a substrate. A first supplier supplies a chemical solution onto the substrate. A first protection plate is provided along an outer circumference of the substrate, to receive the chemical solution splashing from the substrate. A second supplier is provided above the first protection plate, to supply a cleaning solution to an inner surface of the first protection plate.
    Type: Application
    Filed: September 7, 2017
    Publication date: August 9, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Takashi Izumi, Fumitoshi Ikegaya
  • Publication number: 20160362793
    Abstract: A semiconductor manufacturing apparatus according to an embodiment comprises a container contains a mixed solution that includes a processing solution for plating processing of a substrate and an additive and being capable of draining a part of the mixed solution when a first condition is satisfied. A first supplier supplies the processing solution to the container. A second supplier supplies the additive to the container when the first condition is satisfied and drainage of a part of the mixed solution is finished.
    Type: Application
    Filed: September 8, 2015
    Publication date: December 15, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takashi IZUMI, Fumitoshi IKEGAYA
  • Publication number: 20150068911
    Abstract: A copper plating apparatus according to an embodiment includes a plating tank configured to have a copper member and a plating member being disposed in an interior of the plating tank, a blocking film configured to partition the interior of the plating tank into an anode chamber where the copper member is to be disposed and a cathode chamber where the plating member is to be disposed, the blocking film being configured to transmit copper ions and not transmit an additive agent, a supply unit configured to supply the additive agent to the anode chamber, and a power supply configured to apply a voltage between the copper member and the plating member.
    Type: Application
    Filed: December 6, 2013
    Publication date: March 12, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Fumitoshi IKEGAYA, Toshiyuki MORITA
  • Patent number: 7526859
    Abstract: The apparatus for manufacturing a wiring substitute comprises a transporter having a circuit where a sheet is circulated; a screen printer for printing a conductive paste on the sheet; a counter for counting the number of times to print the conductive paste on the sheet; and a distributor for ejecting the sheet from the circuit when the counted number reaches a preset number. Thus, the conductive pillars having uniform properties can be formed automatically on the conductive foil with high productivity.
    Type: Grant
    Filed: October 13, 2006
    Date of Patent: May 5, 2009
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Kenji Sasaoka, Fumitoshi Ikegaya, Takahiro Mori, Tomohisa Motomura, Yoshizumi Sato, Koichiro Shibayama
  • Publication number: 20070044294
    Abstract: The apparatus for manufacturing a wiring substitute comprises a transporter having a circuit where a sheet is circulated; a screen printer for printing a conductive paste on the sheet; a counter for counting the number of times to print the conductive paste on the sheet; and a distributor for ejecting the sheet from the circuit when the counted number reaches a preset number. Thus, the conductive pillars having uniform properties can be formed automatically on the conductive foil with high productivity.
    Type: Application
    Filed: October 13, 2006
    Publication date: March 1, 2007
    Applicant: Dai Nippon Printing Co., Ltd.
    Inventors: Kenji Sasaoka, Fumitoshi Ikegaya, Takahiro Mori, Tomohisa Motomura, Yoshizumi Sato, Koichiro Shibayama
  • Patent number: 7134193
    Abstract: The apparatus for manufacturing a wiring substitute comprises a transporter having a circuit where a sheet is circulated; a screen printer for printing a conductive paste on the sheet; a counter for counting the number of times to print the conductive paste on the sheet; and a distributor for ejecting the sheet from the circuit when the counted number reaches a preset number. Thus, the conductive pillars having uniform properties can be formed automatically on the conductive foil with high productivity.
    Type: Grant
    Filed: December 29, 2004
    Date of Patent: November 14, 2006
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Kenji Sasaoka, Fumitoshi Ikegaya, Takahiro Mori, Tomohisa Motomura, Yoshizumi Sato, Koichiro Shibayama
  • Publication number: 20050272258
    Abstract: According to one aspect of the present invention, provided is a method of manufacturing a semiconductor device, including: forming a first metal film on a substrate having a recessed portion in a surface thereof, by a plating method so as to bury the first metal film in at least part of the recessed portion; forming a second metal film on the first metal film by a film deposition method different from the plating method, the second metal film including, as a main component, a metal that is a main component of the first metal film and containing an impurity whose concentration is lower than concentration of an impurity contained in the first metal film; heat-treating the first and second metal films; and removing the first and second metal films except portions buried in the recessed portion.
    Type: Application
    Filed: June 3, 2005
    Publication date: December 8, 2005
    Inventors: Toshiyuki Morita, Hiroshi Toyoda, Yoshitaka Matsui, Fumitoshi Ikegaya, Atsuko Sakata, Tomio Katata, Seiichi Omoto
  • Publication number: 20050115068
    Abstract: The apparatus for manufacturing a wiring substitute comprises a transporter having a circuit where a sheet is circulated; a screen printer for printing a conductive paste on the sheet; a counter for counting the number of times to print the conductive paste on the sheet; and a distributor for ejecting the sheet from the circuit when the counted number reaches a preset number. Thus, the conductive pillars having uniform properties can be formed automatically on the conductive foil with high productivity.
    Type: Application
    Filed: December 29, 2004
    Publication date: June 2, 2005
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kenji Sasaoka, Fumitoshi Ikegaya, Takahiro Mori, Tomohisa Motomura, Yoshizumi Sato, Koichiro Shibayama
  • Patent number: 6865801
    Abstract: The apparatus for manufacturing a wiring substitute comprises a transporter having a circuit where a sheet is circulated; a screen printer for printing a conductive paste on the sheet; a counter for counting the number of times to print the conductive paste on the sheet; and a distributor for ejecting the sheet from the circuit when the counted number reaches a preset number. Thus, the conductive pillars having uniform properties can be formed automatically on the conductive foil with high productivity.
    Type: Grant
    Filed: July 5, 2001
    Date of Patent: March 15, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenji Sasaoka, Fumitoshi Ikegaya, Takahiro Mori, Tomohisa Motomura, Yoshizumi Sato, Koichiro Shibayama
  • Patent number: 6507995
    Abstract: The apparatus for manufacturing a wiring substitute comprises a transporter having a circuit where a sheet is circulated; a screen printer for printing a conductive paste on the sheet; a counter for counting the number of times to print the conductive paste on the sheet; and a distributor for ejecting the sheet from the circuit when the counted number reaches a preset number. Thus, the conductive pillars having uniform properties can be formed automatically on the conductive foil with high productivity.
    Type: Grant
    Filed: June 9, 1998
    Date of Patent: January 21, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenji Sasaoka, Fumitoshi Ikegaya, Takahiro Mori, Tomohisa Motomura, Yoshizumi Sato, Koichiro Shibayama
  • Publication number: 20010039720
    Abstract: The apparatus for manufacturing a wiring substitute comprises a transporter having a circuit where a sheet is circulated; a screen printer for printing a conductive paste on the sheet; a counter for counting the number of times to print the conductive paste on the sheet; and a distributor for ejecting the sheet from the circuit when the counted number reaches a preset number. Thus, the conductive pillars having uniform properties can be formed automatically on the conductive foil with high productivity.
    Type: Application
    Filed: July 5, 2001
    Publication date: November 15, 2001
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kenji Sasaoka, Fumitoshi Ikegaya, Takahiro Mori, Tomohisa Motomura, Yoshizumi Sato, Koichiro Shibayama
  • Patent number: 6010769
    Abstract: A multilayered wiring board using conductive pillars for the interconnection of wiring layers. Since through holes are bored in the via lands of the wiring layers of the multilayered wiring board, the stress applied between the conductive pillars and wiring layers can be released at the time of connecting the conductive pillars to the via lands. Since the external side face of each conductive pillar smoothly continues to the surface of the via land at the contact section between the conductive pillar and the via land, the notch effect is relieved. Therefore, the reliability of the interconnection is secured even when a stress is applied to the connections during the manufacturing of the multilayered wiring board, and the mounting of electronic elements, etc.
    Type: Grant
    Filed: July 16, 1997
    Date of Patent: January 4, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenji Sasaoka, Hiroshi Odaira, Madoka Fujiwara, Fumitoshi Ikegaya, Takahiro Mori
  • Patent number: 5822850
    Abstract: A supporting member or first synthetic resin sheet with conductive bumps disposed at predetermined positions are superposed on a second synthetic resin sheet under the condition that the resin component of the second synthetic resin sheet is plastic deformed or the temperature thereof exceeds a glass transition temperature so that the conductive bumps are pierced into the second synthetic resin sheet. In other words, the conductive bumps are pierced vertically into the second synthetic resin sheet so as to form through-type conducive lead portions exposed to the first (supporting substrate) and second synthetic resin sheets. The through-type conductive lead portions are used to electrically connect electric devices and circuit and to connect wiring pattern layers. The conductive bumps can be precisely and densely formed and disposed by printing method or plating method. The conductive bumps can be pushed and pierced into the second synthetic resin sheet.
    Type: Grant
    Filed: December 22, 1995
    Date of Patent: October 20, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Odaira, Eiji Imamura, Yusuke Wada, Yasushi Arai, Kenji Sasaoka, Takahiro Mori, Fumitoshi Ikegaya, Sadao Kowatari
  • Patent number: 5600103
    Abstract: A supporting member or first synthetic resin sheet with conductive bumps disposed at predetermined positions are superposed on a second synthetic resin sheet under the condition that the resin component of the second synthetic resin sheet is plastic deformed or the temperature thereof exceeds a glass transition temperature so that the conductive bumps are pierced into the second synthetic resin sheet. In other words, the conductive bumps are pierced vertically into the second synthetic resin sheet so as to form through-type conducive lead portions exposed to the first (supporting substrate) and second synthetic resin sheets. The through-type conductive lead portions are used to electrically connect electric devices and circuit and to connect wiring pattern layers. The conductive bumps can be precisely and densely formed and disposed by printing method or plating method. The conductive bumps can be pushed and pierced into the second synthetic resin sheet.
    Type: Grant
    Filed: March 2, 1994
    Date of Patent: February 4, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Odaira, Eiji Imamura, Yusuke Wada, Yasushi Arai, Kenji Sasaoka, Takahiro Mori, Fumitoshi Ikegaya, Sadao Kowatari