Abstract: A set of memory cells can be erased by individually erasing portions of the set in order to normalize the erase behavior of each memory cell and provide more consistent erase rates. An erase voltage pulse can be applied to the set of memory cells with a first group of cells biased for erase and a second group biased to inhibit erase. A second erase voltage pulse can then be applied with the second group biased for erase and the first group biased to inhibit erase. The groups are chosen so that the erase potentials for the cells in the first subset during the first pulse are about equal, so that the erase potentials for the cells in the second subset during the second pulse are about equal, and so that the erase potentials for the cells of the first subset are about the same as the erase potentials for the cells of the second subset.

Abstract: A system is capable of performing a processing flow based on a definition file which designates a plurality of tasks each of which can be performed by a function provided by an image forming apparatus and an order of performance of a plurality of tasks. The system includes an acquisition unit configured to acquire a definition file of the processing flow specified by a user, a determination unit configured to select one of a plurality of image forming apparatuses to perform each task included in the processing flow based on candidate information included in the definition file of the processing flow, and a performing unit configured to perform each task included in the processing flow using the image forming apparatus selected by the determination unit. The candidate information includes information on a user device that is set corresponding to each user as information for determining the image forming apparatus that performs the task.

Abstract: Non-volatile storage elements are programmed in a manner that reduces program disturb, particularly at the edges storage elements strings, by using modified pass voltages. In particular, during the programming of a selected storage element, an isolation voltage is applied to a storage element proximate to the selected storage element thereby electrically dividing the channel associated with the storage elements into two isolated areas. Additional isolated areas are formed remotely from the selected storage element by applying the isolation voltage to other remote storage elements. The isolated channel regions associated with the storage elements are then boosted with different pass voltages in order to alleviate the effects of program disturb. Thus, a standard pass voltage is applied to storage elements immediately adjacent to the selected storage element, and a lower pass voltage is applied to storage elements remote from the selected storage element.

Abstract: The degree of integration and the number of rewriting of a semiconductor device having a nonvolatile memory element are improved. A first MONOS nonvolatile-memory-element and a second MONOS nonvolatile-memory-element having a large gate width compared with the first MONOS nonvolatile-memory-element are mounted together on the same substrate, and the first MONOS nonvolatile-memory-element is used for storing program data which is scarcely rewritten, and the second MONOS nonvolatile-memory-element is used for storing processed data which is frequently rewritten.

Abstract: The present invention improves security of image data when communication between an image managing apparatus that stores the image data of a submitted job and an image processing apparatus is not possible. To accomplish this, for executing a specific process according to a submitted job, the image data and log information of the job is transmitted to the image managing apparatus to store them when the image processing apparatus can communicate with the image managing apparatus. After transmission of the image data and the log information, upon receiving a notification indicating the completion of storage from the image managing apparatus, control is made to execute a specific process on the image data.

Abstract: A set of memory cells can be erased by individually erasing portions of the set in order to normalize the erase behavior of each memory cell and provide more consistent erase rates. An erase voltage pulse can be applied to the set of memory cells with a first group of cells biased for erase and a second group biased to inhibit erase. A second erase voltage pulse can then be applied with the second group biased for erase and the first group biased to inhibit erase. The groups are chosen so that the erase potentials for the cells in the first subset during the first pulse are about equal, so that the erase potentials for the cells in the second subset during the second pulse are about equal, and so that the erase potentials for the cells of the first subset are about the same as the erase potentials for the cells of the second subset.

Abstract: Soft programming is performed to narrow the threshold voltage distribution of a set of erased memory cells. Soft programming can shift the threshold voltage of memory cells closer to a verify level for the erased state. A set of memory cells can be soft programmed by soft programming portions of the set to provide more consistent soft programming rates and threshold voltages. A first soft programming pulse can be applied to a first group of cells of the set while inhibiting soft programming of a second group of cells. A second soft programming pulse can then be applied to the second group of cells while inhibiting soft programming of the first group of cells. A small positive voltage of lower magnitude than the soft programming pulses can be applied to the group of cells to be inhibited. The size of the small positive voltage can be chosen so that each memory cell of the set will experience similar capacitive coupling effects from neighboring transistors when it is undergoing soft programming.

Abstract: A set of memory cells can be erased by individually erasing portions of the set in order to normalize the erase behavior of each memory cell and provide more consistent erase rates. An erase voltage pulse can be applied to the set of memory cells with a first group of cells biased for erase and a second group biased to inhibit erase. A second erase voltage pulse can then be applied with the second group biased for erase and the first group biased to inhibit erase. The groups are chosen so that the erase potentials for the cells in the first subset during the first pulse are about equal, so that the erase potentials for the cells in the second subset during the second pulse are about equal, and so that the erase potentials for the cells of the first subset are about the same as the erase potentials for the cells of the second subset.

Abstract: Soft programming is performed to narrow the threshold voltage distribution of a set of erased memory cells. Soft programming can shift the threshold voltage of memory cells closer to a verify level for the erased state. A set of memory cells can be soft programmed by soft programming portions of the set to provide more consistent soft programming rates and threshold voltages. A first soft programming pulse can be applied to a first group of cells of the set while inhibiting soft programming of a second group of cells. A second soft programming pulse can then be applied to the second group of cells while inhibiting soft programming of the first group of cells. A small positive voltage of lower magnitude than the soft programming pulses can be applied to the group of cells to be inhibited. The size of the small positive voltage can be chosen so that each memory cell of the set will experience similar capacitive coupling effects from neighboring transistors when it is undergoing soft programming.

Abstract: A substrate of a non-volatile storage system includes selected regions in which additional ions are deeply implanted during the fabrication process. NAND strings are formed over the selected regions such that end word lines of the NAND strings are over the deeply implanted ions. The presence of the deeply implanted ions below the end word lines increases a channel capacitance of the substrate under the end word lines. Due to the increased capacitance, boosting of a channel in the substrate below the end word lines is reduced, thereby reducing the occurrence of gate induced drain leakage (GIDL) and band-to-band tunneling (BTBT) and, consequently, program disturb. A shallow ion implantation may also be made to set a threshold voltage of storage elements of the NAND string.

Abstract: A substrate of a non-volatile storage system includes selected regions in which additional ions are deeply implanted during the fabrication process. NAND strings are formed over the selected regions such that end word lines of the NAND strings are over the deeply implanted ions. The presence of the deeply implanted ions below the end word lines increases a channel capacitance of the substrate under the end word lines. Due to the increased capacitance, boosting of a channel in the substrate below the end word lines is reduced, thereby reducing the occurrence of gate induced drain leakage (GIDL) and band-to-band tunneling (BTBT) and, consequently, program disturb. A shallow ion implantation may also be made to set a threshold voltage of storage elements of the NAND string.

Abstract: The degree of integration and the number of rewriting of a semiconductor device having a nonvolatile memory element are improved. A first MONOS nonvolatile-memory-element and a second MONOS nonvolatile-memory-element having a large gate width compared with the first MONOS nonvolatile-memory-element are mounted together on the same substrate, and the first MONOS nonvolatile-memory-element is used for storing program data which is scarcely rewritten, and the second MONOS nonvolatile-memory-element is used for storing processed data which is frequently rewritten.

Abstract: An image-forming apparatus configured to be controlled based on access-control information and to perform a flow which includes performance a plurality of functions of the image forming apparatus based on flow setting information, where flow setting information designates an order of performance of the plurality of functions of the image forming apparatus. The image-forming apparatus includes an acquisition unit configured to acquire the access-control information based on a signature included in the flow setting information if the flow setting information includes the signature, and a flow-performing unit configured to perform the flow based on the access-control information acquired by the acquisition unit.

Abstract: Non-volatile storage elements are programmed in a manner that reduces program disturb, particularly at the edges storage elements strings, by using modified pass voltages. In particular, during the programming of a selected storage element, an isolation voltage is applied to a storage element proximate to the selected storage element thereby electrically dividing the channel associated with the storage elements into two isolated areas. Additional isolated areas are formed remotely from the selected storage element by applying the isolation voltage to other remote storage elements. The isolated channel regions associated with the storage elements are then boosted with different pass voltages in order to alleviate the effects of program disturb. Thus, a standard pass voltage is applied to storage elements immediately adjacent to the selected storage element, and a lower pass voltage is applied to storage elements remote from the selected storage element.

Abstract: An image copying device includes: a setting section setting an image processing condition specified by a user; a determination section determining whether or not an image processing condition is embedded in a read image obtained by reading out a sheet; and a control section that, if the determination section determines that the image processing condition is not embedded in the read image, performs control for generating a copied material of the read image by using the image processing condition set by the setting section. If the determination section determines that an image processing condition is embedded in the read image, the control section performs control for generating a copied material by using the embedded image processing condition and a part of the image processing condition set by the setting section, the part not conflicting with the embedded image processing condition.

Abstract: A semiconductor device has a nonvolatile memory employing a split-gate type memory cell structure, using a nitride film as a charge storage layer. An n-type semiconductor region is formed in a main surface of a semiconductor substrate, and then, a memory gate electrode of a memory cell of a split gate type and a charge storage layer are formed over the semiconductor region. Subsequently, side walls are formed on side surfaces of the memory gate electrode, and a photoresist pattern is formed over the main surface of the semiconductor substrate. The photoresist pattern serves as an etching mask, and a part of the main surface of the semiconductor substrate is removed by etching to form a dent. In the region of the dent, the n-type semiconductor region is removed. Then, a p-type semiconductor region for forming a channel of an nMIS transistor for selecting a memory cell is formed.

Abstract: A two-type gate process is suitable for forming a gate insulation film partially formed of a high dielectric film, for example, a titanium oxide film (gate insulation film of the internal circuit) having a relative dielectric constant larger than that of silicon nitride on a substrate, and a silicon nitride film is deposited on the titanium oxide film. The silicon nitride film will prevent oxidation of the titanium oxide film when the surface of the substrate is subjected to thermal oxidation in the next process step. Next, the silicon nitride film and the titanium oxide film on the I/O circuit region are removed, while the silicon nitride film and the titanium oxide film on the internal circuit region remain, and the substrate is subjected to thermal oxidation to form a silicon oxide film as a gate insulation film on the surface of the I/O circuit region.

Abstract: The degree of integration and the number of rewriting of a semiconductor device having a nonvolatile memory element are improved. A first MONOS nonvolatile-memory-element and a second MONOS nonvolatile-memory-element having a large gate width compared with the first MONOS nonvolatile-memory-element are mounted together on the same substrate, and the first MONOS nonvolatile-memory-element is used for storing program data which is scarcely rewritten, and the second MONOS nonvolatile-memory-element is used for storing processed data which is frequently rewritten.

Abstract: A method for quantitatively analyzing a wafer for metal impurities is disclosed, wherein the wafer has first and second surfaces. The method includes heating the first surface of the wafer to diffuse the metal impurities to the second surface in an environment at least substantially free of contamination, cooling the first surface of the wafer, and quantitatively analyzing the second surface of the wafer for the metal impurities.

Abstract: A semiconductor device has a nonvolatile memory employing a split-gate type memory cell structure, using a nitride film as a charge storage layer. An n-type semiconductor region is formed in a main surface of a semiconductor substrate, and then, a memory gate electrode of a memory cell of a split gate type and a charge storage layer are formed over the semiconductor region. Subsequently, side walls are formed on side surfaces of the memory gate electrode, and a photoresist pattern is formed over the main surface of the semiconductor substrate. The photoresist pattern serves as an etching mask, and a part of the main surface of the semiconductor substrate is removed by etching to form a dent. In the region of the dent, the n-type semiconductor region is removed. Then, a p-type semiconductor region for forming a channel of an nMIS transistor for selecting a memory cell is formed.