Patents by Inventor Fumiya Kimura
Fumiya Kimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240088192Abstract: The present invention provides a technology which realizes a reliable semiconductor device including a photosensor device by preventing pent roofs of edges of a P+ layer from being generated and a metal wiring installed over the P+ layer from coming down while securing the electrical conductivity of the P+ layer. The semiconductor device includes a photosensor including a photodiode formed on a substrate. The photodiode includes: a cathode electrode; a laminated structure that is formed on the cathode electrode and in which an N+ layer, an I layer, and a P+ layer are laminated in this order; an anode electrode formed on the P+ layer; a first insulating film formed so as to cover a portion of the anode electrode and edges of the laminated structure; and a metal wiring connected to the anode electrode. The edges of the laminated structure are formed in forward tapered shapes in a cross-sectional view.Type: ApplicationFiled: November 21, 2023Publication date: March 14, 2024Applicant: Japan Display Inc.Inventors: Hajime WATAKABE, Akihiro HANADA, Marina MOCHIZUKI, Ryo ONODERA, Fumiya KIMURA, Isao SUZUMURA
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Patent number: 11906862Abstract: According to one embodiment, a display device includes a semiconductor layer, a first insulating layer, a gate electrode, a second insulating layer and a plurality of transparent conductive layers. The transparent conductive layers include a pixel electrode, a first conductive layer and a second conductive layer. The pixel electrode is in contact with the second conductive layer. The second conductive layer is in contact with the first conductive layer. The first conductive layer is brought into contact with a second region of the semiconductor layer through a first contact hole.Type: GrantFiled: October 4, 2022Date of Patent: February 20, 2024Assignee: JAPAN DISPLAY INC.Inventors: Isao Suzumura, Fumiya Kimura, Kazuhide Mochizuki, Hitoshi Tanaka, Kenichi Akutsu, Atsuko Shimada
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Patent number: 11874574Abstract: According to one embodiment, a display device includes a signal line, a scanning line, a semiconductor layer, a first insulating layer which covers the semiconductor layer, a color filter above the first insulating layer, a pixel electrode above the color filter and a common electrode. The first insulating layer includes a first contact hole for connecting the semiconductor layer and the pixel electrode to each other. The first contact hole is provided at a position displaced from the color filter in plan view.Type: GrantFiled: December 21, 2022Date of Patent: January 16, 2024Assignee: JAPAN DISPLAY INC.Inventors: Fumiya Kimura, Isao Suzumura
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Patent number: 11855117Abstract: The present invention provides a technology which realizes a reliable semiconductor device including a photosensor device by preventing pent roofs of edges of a P+ layer from being generated and a metal wiring installed over the P+ layer from coming down while securing the electrical conductivity of the P+ layer. The semiconductor device includes a photosensor including a photodiode formed on a substrate. The photodiode includes: a cathode electrode; a laminated structure that is formed on the cathode electrode and in which an N+ layer, an I layer, and a P+ layer are laminated in this order; an anode electrode formed on the P+ layer; a first insulating film formed so as to cover a portion of the anode electrode and edges of the laminated structure; and a metal wiring connected to the anode electrode. The edges of the laminated structure are formed in forward tapered shapes in a cross-sectional view.Type: GrantFiled: February 4, 2021Date of Patent: December 26, 2023Assignee: JAPAN DISPLAY INC.Inventors: Hajime Watakabe, Akihiro Hanada, Marina Mochizuki, Ryo Onodera, Fumiya Kimura, Isao Suzumura
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Patent number: 11822194Abstract: According to one embodiment, a display device includes a semiconductor layer, a first insulating layer, a gate electrode, a second insulating layer, a third insulating layer, a color filter, and transparent conductive layers including a pixel electrode, a first conductive layer, and a second conductive layer. The first conductive layer is located between the second insulating layer and the third insulating layer, and is in contact with a second area of the semiconductor layer. The second conductive layer is located on the color filter and is in contact with the first conductive layer. The pixel electrode is located on the second conductive layer and is in contact with the second conductive layer.Type: GrantFiled: May 20, 2022Date of Patent: November 21, 2023Assignee: Japan Display Inc.Inventors: Fumiya Kimura, Isao Suzumura, Junko Nagasawa, Atsuko Imoto
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Publication number: 20230280623Abstract: A display device is provided and includes a substrate on which a TFT is formed. The display device including an organic film formed on the TFT, the organic film having a through hole, and a first common electrode, an upper pixel electrode and a second common electrode which are stacked in this order above the organic passivation film, a filler being filled in the through hole, and wherein the upper pixel electrode is electrically connected with the TFT, and an edge of the upper pixel electrode is located directly on the filler.Type: ApplicationFiled: May 11, 2023Publication date: September 7, 2023Inventors: Fumiya KIMURA, Isao SUZUMURA
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Publication number: 20230284509Abstract: According to one embodiment, a display device manufacturing method comprises forming a lower electrode including a first metal layer and a conductive oxide layer which covers the first metal layer and which has a thickness of 15 nm or more and 50 nm or less, forming a rib covering at least a part of the lower electrode and including a pixel aperture which exposes the conductive oxide layer, forming a second metal layer above the rib and the conductive oxide layer exposed through the pixel aperture, and patterning the second metal layer by etching including wet etching to form a partition on the rib.Type: ApplicationFiled: February 28, 2023Publication date: September 7, 2023Applicant: Japan Display Inc.Inventors: Isao SUZUMURA, Fumiya KIMURA, Hiroshi OGAWA
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Publication number: 20230205023Abstract: According to one embodiment, a display device includes a signal line, a scanning line, a semiconductor layer, a first insulating layer which covers the semiconductor layer, a color filter above the first insulating layer, a pixel electrode above the color filter and a common electrode. The first insulating layer includes a first contact hole for connecting the semiconductor layer and the pixel electrode to each other. The first contact hole is provided at a position displaced from the color filter in plan view.Type: ApplicationFiled: December 21, 2022Publication date: June 29, 2023Applicant: Japan Display Inc.Inventors: Fumiya KIMURA, Isao SUZUMURA
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Patent number: 11656514Abstract: The purpose of the present invention is to obviate patterning defects of electrodes in through-holes formed in an organic passivation film for connection between TFTs and pixel electrodes in an ultra-high definition display device. To achieve the foregoing, the present invention has a configuration such as the following. This display device, in which a TFT (thin-film transistor) is formed on a substrate, an organic passivation film is formed covering the TFT, and a first pixel electrode, a first common electrode, a second pixel electrode, and a second common electrode are formed on the organic passivation film, is characterized in that the first pixel electrode is connected to the TFT via a through-hole formed in the organic passivation film, the through-hole is filled with a filler, and an end of the second pixel electrode is present on the upper side of the filler.Type: GrantFiled: June 28, 2022Date of Patent: May 23, 2023Assignee: Japan Display Inc.Inventors: Fumiya Kimura, Isao Suzumura
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Publication number: 20230026937Abstract: According to one embodiment, a display device includes a semiconductor layer, a first insulating layer, a gate electrode, a second insulating layer and a plurality of transparent conductive layers. The transparent conductive layers include a pixel electrode, a first conductive layer and a second conductive layer. The pixel electrode is in contact with the second conductive layer. The second conductive layer is in contact with the first conductive layer. The first conductive layer is brought into contact with a second region of the semiconductor layer through a first contact hole.Type: ApplicationFiled: October 4, 2022Publication date: January 26, 2023Applicant: Japan Display Inc.,Inventors: Isao SUZUMURA, Fumiya KIMURA, Kazuhide MOCHIZUKI, Hitoshi TANAKA, Kenichi AKUTSU, Atsuko SHIMADA
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Publication number: 20220376076Abstract: A semiconductor device includes a substrate, an oxide semiconductor layer over the substrate, a gate insulating layer over the oxide semiconductor layer, a metal oxide layer over the gate insulating layer, and a gate electrode over the metal oxide layer. A first side surface of the metal oxide protrudes from a second side surface of the gate electrode in a plan view.Type: ApplicationFiled: May 17, 2022Publication date: November 24, 2022Applicant: Japan Display Inc.Inventors: Toshiki KANEKO, Fumiya KIMURA
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Publication number: 20220373846Abstract: According to one embodiment, a display device includes a semiconductor layer, a first insulating layer, a gate electrode, a second insulating layer, a third insulating layer, a color filter, and transparent conductive layers including a pixel electrode, a first conductive layer, and a second conductive layer. The first conductive layer is located between the second insulating layer and the third insulating layer, and is in contact with a second area of the semiconductor layer. The second conductive layer is located on the color filter and is in contact with the first conductive layer. The pixel electrode is located on the second conductive layer and is in contact with the second conductive layer.Type: ApplicationFiled: May 20, 2022Publication date: November 24, 2022Inventors: Fumiya KIMURA, Isao SUZUMURA, Junko NAGASAWA, Atsuko IMOTO
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Patent number: 11493812Abstract: According to one embodiment, a display device includes a semiconductor layer, a first insulating layer, a gate electrode, a second insulating layer and a plurality of transparent conductive layers. The transparent conductive layers include a pixel electrode, a first conductive layer and a second conductive layer. The pixel electrode is in contact with the second conductive layer. The second conductive layer is in contact with the first conductive layer. The first conductive layer is brought into contact with a second region of the semiconductor layer through a first contact hole.Type: GrantFiled: October 9, 2020Date of Patent: November 8, 2022Assignee: JAPAN DISPLAY INC.Inventors: Isao Suzumura, Fumiya Kimura, Kazuhide Mochizuki, Hitoshi Tanaka, Kenichi Akutsu, Atsuko Shimada
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Publication number: 20220326581Abstract: The purpose of the present invention is to obviate patterning defects of electrodes in through-holes formed in an organic passivation film for connection between TFTs and pixel electrodes in an ultra-high definition display device. To achieve the foregoing, the present invention has a configuration such as the following. This display device, in which a TFT (thin-film transistor) is formed on a substrate, an organic passivation film is formed covering the TFT, and a first pixel electrode, a first common electrode, a second pixel electrode, and a second common electrode are formed on the organic passivation film, is characterized in that the first pixel electrode is connected to the TFT via a through-hole formed in the organic passivation film, the through-hole is filled with a filler, and an end of the second pixel electrode is present on the upper side of the filler.Type: ApplicationFiled: June 28, 2022Publication date: October 13, 2022Inventors: Fumiya KIMURA, Isao SUZUMURA
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Publication number: 20210257402Abstract: The present invention provides a technology which realizes a reliable semiconductor device including a photosensor device by preventing pent roofs of edges of a P+ layer from being generated and a metal wiring installed over the P+ layer from coming down while securing the electrical conductivity of the P+ layer. The semiconductor device includes a photosensor including a photodiode formed on a substrate. The photodiode includes: a cathode electrode; a laminated structure that is formed on the cathode electrode and in which an N+ layer, an I layer, and a P+ layer are laminated in this order; an anode electrode formed on the P+ layer; a first insulating film formed so as to cover a portion of the anode electrode and edges of the laminated structure; and a metal wiring connected to the anode electrode. The edges of the laminated structure are formed in forward tapered shapes in a cross-sectional view.Type: ApplicationFiled: February 4, 2021Publication date: August 19, 2021Applicant: Japan Display Inc.Inventors: Hajime WATAKABE, Akihiro HANADA, Marina MOCHIZUKI, Ryo ONODERA, Fumiya KIMURA, Isao SUZUMURA
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Publication number: 20210109412Abstract: According to one embodiment, a display device includes a semiconductor layer, a first insulating layer, a gate electrode, a second insulating layer and a plurality of transparent conductive layers. The transparent conductive layers include a pixel electrode, a first conductive layer and a second conductive layer. The pixel electrode is in contact with the second conductive layer. The second conductive layer is in contact with the first conductive layer. The first conductive layer is brought into contact with a second region of the semiconductor layer through a first contact hole.Type: ApplicationFiled: October 9, 2020Publication date: April 15, 2021Applicant: Japan Display Inc.,Inventors: Isao SUZUMURA, Fumiya KIMURA, Kazuhide MOCHIZUKI, Hitoshi TANAKA, Kenichi AKUTSU, Atsuko SHIMADA
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Patent number: 6448489Abstract: A solar generation system includes a standard solar cell string and a substandard solar cell string. A DC voltage output from the substandard solar cell string is boosted by a booster unit to the level of the DC voltage output from the standard solar cell string, and the DC voltage from the standard solar cell string and the boosted DC voltage are applied to a DC/AC inverter, whereby an AC power is obtained, which is supplied to a utility power supply.Type: GrantFiled: April 27, 2001Date of Patent: September 10, 2002Assignee: Sharp Kabushiki KaishaInventors: Fumiya Kimura, Hirofumi Nakata, Tsukasa Takebayashi, Hirokazu Kodama, Kiyoshi Nishida
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Publication number: 20010035180Abstract: A solar generation system includes a standard solar cell string and a substandard solar cell string. A DC voltage output from the substandard solar cell string is boosted by a booster unit to the level of the DC voltage output from the standard solar cell string, and the DC voltage from the standard solar cell string and the boosted DC voltage are applied to a DC/AC inverter, whereby an AC power is obtained, which is supplied to a utility power supply.Type: ApplicationFiled: April 27, 2001Publication date: November 1, 2001Inventors: Fumiya Kimura, Hirofumi Nakata, Tsukasa Takebayashi, Hirokazu Kodama, Kiyoshi Nishida