Abstract: To solve the problem of conventional image sensing devices that require much time for reading pixel signals, an image sensing device according to an embodiment includes a first pixel unit coupled to a first vertical read line, a second pixel unit coupled to a second vertical read line and placed in the column of the first pixel unit, a first transfer switch provided at an end of the first read line, and a second transfer switch provided at an end of the second read line. When the first transfer switch is controlled to be closed and the second transfer switch is controlled to be conductive, the image sensing device performs a reset process of the vertical read line by a dark level signal output from the second pixel unit, and a conversion process of the dark level read from the first pixel unit, and the pixel signal into digital values.

Abstract: To solve the problem of conventional image sensing devices that require much time for reading pixel signals, an image sensing device according to an embodiment includes a first pixel unit coupled to a first vertical read line, a second pixel unit coupled to a second vertical read line and placed in the column of the first pixel unit, a first transfer switch provided at an end of the first read line, and a second transfer switch provided at an end of the second read line. When the first transfer switch is controlled to be closed and the second transfer switch is controlled to be conductive, the image sensing device performs a reset process of the vertical read line by a dark level signal output from the second pixel unit, and a conversion process of the dark level read from the first pixel unit, and the pixel signal into digital values.

Abstract: There is provided a solid-state image pickup device including ADCs that can be arranged in a limited space. The potential of a pixel signal outputted through a vertical readout line is held at a node. A plurality of capacitors are capacitively coupled to the node at which the pixel signal is held. The potential of the node is decreased in a stepwise manner by sequentially switching the voltages of the counter electrodes of the capacitors by the control of transistors. A comparator compares the potential of the node with the potential of the dark state of the pixel, and determines the upper bits of a digital value when the potential of the node becomes lower than the potential of the dark state. Following this, the conversion of the lower bits of the digital value is started. Therefore, it is possible to simplify the configuration of each ADC and arrange each ADC in a limited space.

Abstract: There is provided a solid-state image pickup device including ADCs that can be arranged in a limited space. The potential of a pixel signal outputted through a vertical readout line is held at a node. A plurality of capacitors are capacitively coupled to the node at which the pixel signal is held. The potential of the node is decreased in a stepwise manner by sequentially switching the voltages of the counter electrodes of the capacitors by the control of transistors. A comparator compares the potential of the node with the potential of the dark state of the pixel, and determines the upper bits of a digital value when the potential of the node becomes lower than the potential of the dark state. Following this, the conversion of the lower bits of the digital value is started. Therefore, it is possible to simplify the configuration of each ADC and arrange each ADC in a limited space.

Abstract: There is provided a solid-state image pickup device including ADCs that can be arranged in a limited space. The potential of a pixel signal outputted through a vertical readout line is held at a node. A plurality of capacitors are capacitively coupled to the node at which the pixel signal is held. The potential of the node is decreased in a stepwise manner by sequentially switching the voltages of the counter electrodes of the capacitors by the control of transistors. A comparator compares the potential of the node with the potential of the dark state of the pixel, and determines the upper bits of a digital value when the potential of the node becomes lower than the potential of the dark state. Following this, the conversion of the lower bits of the digital value is started. Therefore, it is possible to simplify the configuration of each ADC and arrange each ADC in a limited space.

Abstract: There is provided a solid-state image pickup device including ADCs that can be arranged in a limited space. The potential of a pixel signal outputted through a vertical readout line is held at a node. A plurality of capacitors are capacitively coupled to the node at which the pixel signal is held. The potential of the node is decreased in a stepwise manner by sequentially switching the voltages of the counter electrodes of the capacitors by the control of transistors. A comparator compares the potential of the node with the potential of the dark state of the pixel, and determines the upper bits of a digital value when the potential of the node becomes lower than the potential of the dark state. Following this, the conversion of the lower bits of the digital value is started. Therefore, it is possible to simplify the configuration of each ADC and arrange each ADC in a limited space.

Abstract: There is provided a solid-state image pickup device including ADCs that can be arranged in a limited space. The potential of a pixel signal outputted through a vertical readout line is held at a node. A plurality of capacitors are capacitively coupled to the node at which the pixel signal is held. The potential of the node is decreased in a stepwise manner by sequentially switching the voltages of the counter electrodes of the capacitors by the control of transistors. A comparator compares the potential of the node with the potential of the dark state of the pixel, and determines the upper bits of a digital value when the potential of the node becomes lower than the potential of the dark state. Following this, the conversion of the lower bits of the digital value is started. Therefore, it is possible to simplify the configuration of each ADC and arrange each ADC in a limited space.

Abstract: There is provided a solid-state image pickup device including ADCs that can be arranged in a limited space. The potential of a pixel signal outputted through a vertical readout line is held at a node. A plurality of capacitors are capacitively coupled to the node at which the pixel signal is held. The potential of the node is decreased in a stepwise manner by sequentially switching the voltages of the counter electrodes of the capacitors by the control of transistors. A comparator compares the potential of the node with the potential of the dark state of the pixel, and determines the upper bits of a digital value when the potential of the node becomes lower than the potential of the dark state. Following this, the conversion of the lower bits of the digital value is started. Therefore, it is possible to simplify the configuration of each ADC and arrange each ADC in a limited space.

Abstract: A semiconductor integrated circuit device provided with a pipeline A-D conversion circuit in which the enhancement of accuracy and the reduction of power consumption are accomplished is provided. The pipeline A-D conversion circuit is connected in series with an input terminal to which an analog signal to be converted is inputted and has a plurality of stages. The stages other than the first stage connected with the input terminal through at least one stage, including the first stage that receives input signals from the input terminal are constructed as follows: each of the other stages is comprised of two or more sample and hold circuits and an amplifier connected in common with the two or more sample and hold circuits. The two or more sample and hold circuits are caused to perform interleave operation.

Abstract: A semiconductor integrated circuit device provided with a pipeline A-D conversion circuit in which the enhancement of accuracy and the reduction of power consumption are accomplished is provided. The pipeline A-D conversion circuit is connected in series with an input terminal to which an analog signal to be converted is inputted and has a plurality of stages. The stages other than the first stage connected with the input terminal through at least one stage, including the first stage that receives input signals from the input terminal are constructed as follows: each of the other stages is comprised of two or more sample and hold circuits and an amplifier connected in common with the two or more sample and hold circuits. The two or more sample and hold circuits are caused to perform interleave operation.

Abstract: A semiconductor integrated circuit device provided with a pipeline A-D conversion circuit in which the enhancement of accuracy and the reduction of power consumption are accomplished is provided. The pipeline A-D conversion circuit is connected in series with an input terminal to which an analog signal to be converted is inputted and has a plurality of stages. The stages other than the first stage connected with the input terminal through at least one stage, including the first stage that receives input signals from the input terminal are constructed as follows: each of the other stages is comprised of two or more sample and hold circuits and an amplifier connected in common with the two or more sample and hold circuits. The two or more sample and hold circuits are caused to perform interleave operation.

Abstract: A semiconductor integrated circuit device provided with a pipeline A-D conversion circuit in which the enhancement of accuracy and the reduction of power consumption are accomplished is provided. The pipeline A-D conversion circuit is connected in series with an input terminal to which an analog signal to be converted is inputted and has a plurality of stages. The stages other than the first stage connected with the input terminal through at least one stage, including the first stage that receives input signals from the input terminal are constructed as follows: each of the other stages is comprised of two or more sample and hold circuits and an amplifier connected in common with the two or more sample and hold circuits. The two or more sample and hold circuits are caused to perform interleave operation.