Abstract: A metal line 731 is formed in a linear area S of an insulative substrate 720, and moreover a metal line 732 is formed generally parallel to the metal line 731 with a specified distance thereto. The metal line 731 is connected to an n-type semiconductor core 701 of bar-like structure light-emitting elements 710A to 710D, and the metal line 732 is connected to a p-type semiconductor layer 702. By dividing the insulative substrate 720 into a plurality of divisional substrates, a plurality of light-emitting devices in each of which a plurality of bar-like structure light-emitting elements 710 are placed on the divisional substrates are formed.

Abstract: A metal line 731 is formed in a linear area S of an insulative substrate 720, and moreover a metal line 732 is formed generally parallel to the metal line 731 with a specified distance thereto. The metal line 731 is connected to an n-type semiconductor core 701 of bar-like structure light-emitting elements 710A to 710D, and the metal line 732 is connected to a p-type semiconductor layer 702. By dividing the insulative substrate 720 into a plurality of divisional substrates, a plurality of light-emitting devices in each of which a plurality of bar-like structure light-emitting elements 710 are placed on the divisional substrates are formed.

Abstract: A display panel (100) is provided which allows optimization of the respective characteristics of different semiconductor elements without incurring an increase in manufacturing cost. The display panel (100) includes: pixel TFTs (11) disposed in a display section (101); scanning driver TFTs (12) disposed in a scanning driver (102); and data driver (13) disposed in a data driver (103). A polysilicon film of the pixel TFTs (11), the scanning driver TFTs (12), and the data driver TFTs (13) is polycrystallized by irradiation of laser light so as to have a crystal growth direction that goes along a scanning direction of the laser light. The pixel TFTs (11) are disposed so that the crystal growth direction of the polysilicon film is substantially perpendicular to the directions of current paths of the pixel TFTs (11).

Abstract: A semiconductor memory device includes: a gate electrode formed on a semiconductor layer via a gate insulating film; a channel region disposed under the gate electrode; diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region; and memory functional units formed on both sides of the gate electrode and having the function of retaining charges, wherein each of the diffusion regions has: a high-concentration impurity region disposed so as to be offset from the gate electrode; and a low-concentration impurity region disposed in contact with the high-concentration impurity region so as to overlap with the gate electrode, and an amount of current flowing from one of the diffusion regions to the other diffusion region is changed when a voltage is applied to the gate electrode in accordance with an amount of charges retained in the memory functional units.

Abstract: A semiconductor memory device includes: a gate electrode formed on a semiconductor layer via a gate insulating film; a channel region disposed under the gate electrode; diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region; and memory functional units formed on both sides of the gate electrode and having the function of retaining charges, wherein each of the diffusion regions has: a high-concentration impurity region disposed so as to be offset from the gate electrode; and a low-concentration impurity region disposed in contact with the high-concentration impurity region so as to overlap with the gate electrode, and an amount of current flowing from one of the diffusion regions to the other diffusion region is changed when a voltage is applied to the gate electrode in accordance with an amount of charges retained in the memory functional units.

Abstract: A gate oxide film (23), a gate electrode (24) and a gate cap insulating film (25) are stacked on an active region of a p-type semiconductor substrate (21), and an insulating side wall (29) is formed, followed by BF2 ion implantation. Thus, a surface of the p-type semiconductor substrate becomes amorphous so that single-crystal silicon is prevented from epitaxially growing in the next process of depositing polysilicon (33). Halo regions (32) are formed using the BF2 ions having the opposite conductivity to a source/drain to reduce the short-channel effect. The substrate is then passed through a nitrogen purge chamber having a dew point kept at −100° C. to remove water molecules completely, and polysilicon (33) is deposited. Because native oxide is prevented from growing at an interface between the active region and the polysilicon, source/drain regions (34) formed later by implantation and diffusion of n-type impurity ions achieve a uniform junction depth.