Patents by Inventor Fumiyuki Kanai
Fumiyuki Kanai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7977234Abstract: A method of fabrication of a semiconductor integrated circuit device, including polishing the entire area of an edge of a wafer, for example, uses three polishing drums in which a polishing drum polishes the upper surface of the edge of the wafer, a polishing drum polishes the central portion of the edge of the wafer and a polishing drum polishes the lower surface of the edge of the wafer, thereby preventing occurrence of obstacles which cause defoliation of thin films on the edge of the wafer.Type: GrantFiled: May 18, 2010Date of Patent: July 12, 2011Assignee: Renesas Electronics CorporationInventors: Toshiyuki Arai, Ryousei Kawai, Hirofumi Tsuchiyama, Fumiyuki Kanai, Shinichi Nakabayashi
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Patent number: 7905562Abstract: To provide a liquid guiding device such that, when liquid is dumped onto a sloping guiding surface portion located in a region where ink is dumped, the liquid is easily guided to an ink absorber and no liquid remains on the guiding surface portion. A guiding surface portion 29 is provided in a liquid dumping region 23 in which ink absorbers 25 and 26 are provided and on the upstream edge of a downstream portion 24 of a platen. The upper surface of the guiding surface portions 29 slopes down toward the upstream side, that is, toward the liquid dumping region 23. In the guiding surface portion 29 is formed a guiding structure portion 31 that guides ink attached to the guiding surface portion to the ink absorber 25. The guiding structure portion may include an edge portion 31 that guides liquid by capillary action. The edge portion may extend to the ink absorbers 25 and 26.Type: GrantFiled: September 11, 2007Date of Patent: March 15, 2011Assignee: Seiko Epson CorporationInventor: Fumiyuki Kanai
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Publication number: 20100227474Abstract: A method of fabrication of a semiconductor integrated circuit device, including polishing the entire area of an edge of a wafer, for example, uses three polishing drums in which a polishing drum polishes the upper surface of the edge of the wafer, a polishing drum polishes the central portion of the edge of the wafer and a polishing drum polishes the lower surface of the edge of the wafer, thereby preventing occurrence of obstacles which cause defoliation of thin films on the edge of the wafer.Type: ApplicationFiled: May 18, 2010Publication date: September 9, 2010Inventors: Toshiyuki ARAI, Ryousei Kawai, Hirofumi Tsuchiyama, Fumiyuki Kanai, Shinichi Nakabayashi
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Patent number: 7718526Abstract: A method of fabrication of a semiconductor integrated circuit device, including polishing the entire area of an edge of a wafer, for example, uses three polishing drums in which a polishing drum polishes the upper surface of the edge of the wafer, a polishing drum polishes the central portion of the edge of the wafer and a polishing drum polishes the lower surface of the edge of the wafer, thereby preventing occurrence of obstacles which cause defoliation of thin films on the edge of the wafer.Type: GrantFiled: July 16, 2007Date of Patent: May 18, 2010Assignee: Renesas Technology CorporationInventors: Toshiyuki Arai, Ryousei Kawai, Hirofumi Tsuchiyama, Fumiyuki Kanai, Shinichi Nakabayashi
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Publication number: 20080106570Abstract: To provide a liquid guiding device such that, when liquid is dumped onto a sloping guiding surface portion located in a region where ink is dumped, the liquid is easily guided to an ink absorber and no liquid remains on the guiding surface portion. A guiding surface portion 29 is provided in a liquid dumping region 23 in which ink absorbers 25 and 26 are provided and on the upstream edge of a downstream portion 24 of a platen. The upper surface of the guiding surface portions 29 slopes down toward the upstream side, that is, toward the liquid dumping region 23. In the guiding surface portion 29 is formed a guiding structure portion 31 that guides ink attached to the guiding surface portion to the ink absorber 25. The guiding structure portion may include an edge portion 31 that guides liquid by capillary action. The edge portion may extend to the ink absorbers 25 and 26.Type: ApplicationFiled: September 11, 2007Publication date: May 8, 2008Applicant: SEIKO EPSON CORPORATIONInventor: Fumiyuki KANAI
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Publication number: 20070259522Abstract: A method of fabrication of a semiconductor integrated circuit device, including polishing the entire area of an edge of a wafer, for example, uses three polishing drums in which a polishing drum polishes the upper surface of the edge of the wafer, a polishing drum polishes the central portion of the edge of the wafer and a polishing drum polishes the lower surface of the edge of the wafer, thereby preventing occurrence of obstacles which cause defoliation of thin films on the edge of the wafer.Type: ApplicationFiled: July 16, 2007Publication date: November 8, 2007Inventors: Toshiyuki Arai, Ryousei Kawai, Hirofumi Tsuchiyama, Fumiyuki Kanai, Shinichi Nakabayashi
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Patent number: 7250365Abstract: A method of fabrication of a semiconductor integrated circuit device, including polishing the entire area of an edge of a wafer, for example, uses three polishing drums in which a polishing drum polishes the upper surface of the edge of the wafer, a polishing drum polishes the central portion of the edge of the wafer and a polishing drum polishes the lower surface of the edge of the wafer, thereby preventing occurrence of obstacles which cause defoliation of thin films on the edge of the wafer.Type: GrantFiled: June 28, 2005Date of Patent: July 31, 2007Assignee: Renesas Technology Corp.Inventors: Toshiyuki Arai, Ryousei Kawai, Hirofumi Tsuchiyama, Fumiyuki Kanai, Shinichi Nakabayashi
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Patent number: 7052995Abstract: A buried film and a barrier film are polished together using a slurry in which the polishing rate on a substrate material (in particular, silicon oxide), that on a buried-film material (in particular, tungsten) and that on a barrier-film material (in particular, titanium oxide) are substantially equal to one another. This can materialize a buried structure free from any step or steps, at a high polishing rate.Type: GrantFiled: June 24, 2002Date of Patent: May 30, 2006Assignee: Renesas Technology Corp.Inventors: Nobuhito Katsumura, Yoshiteru Katsumura, Hidemi Sato, Norihiro Uchida, Fumiyuki Kanai
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Patent number: 6979649Abstract: A method of fabrication of a semiconductor integrated circuit device, including polishing the entire area of an edge of a wafer, for example, uses three polishing drums in which a polishing drum polishes the upper surface of the edge of the water, a polishing drum polishes the central portion of the edge of the wafer and a polishing drum polishes the lower surface of the edges of the wafer, thereby preventing occurrence of obstacles which cause defoliation of thin films on the edge of the wafer.Type: GrantFiled: March 1, 2002Date of Patent: December 27, 2005Assignee: Renesas Technology Corp.Inventors: Toshiyuki Arai, Ryousei Kawai, Hirofumi Tsuchiyama, Fumiyuki Kanai, Shinichi Nakabayashi
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Publication number: 20050250331Abstract: A method of fabrication of a semiconductor integrated circuit device, including polishing the entire area of an edge of a wafer, for example, uses three polishing drums in which a polishing drum polishes the upper surface of the edge of the wafer, a polishing drum polishes the central portion of the edge of the wafer and a polishing drum polishes the lower surface of the edge of the wafer, thereby preventing occurrence of obstacles which cause defoliation of thin films on the edge of the wafer.Type: ApplicationFiled: June 28, 2005Publication date: November 10, 2005Inventors: Toshiyuki Arai, Ryousei Kawai, Hirofumi Tsuchiyama, Fumiyuki Kanai, Shinichi Nakabayashi
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Publication number: 20030025200Abstract: A buried film and a barrier film are polished together using a slurry in which the polishing rate on a substrate material (in particular, silicon oxide), that on a buried-film material (in particular, tungsten) and that on a barrier-film material (in particular, titanium oxide) are substantially equal to one another. This can materialize a buried structure free from any step or steps, at a high polishing rate.Type: ApplicationFiled: June 24, 2002Publication date: February 6, 2003Inventors: Nobuhito Katsumura, Yoshiteru Katsumura, Hidemi Sato, Norihiro Uchida, Fumiyuki Kanai
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Patent number: 6512245Abstract: A static random access memory comprising memory cells each composed of transfer MISFETs controlled by word lines and of a flip-flop circuit made of driver MISFETs and load MISFETs. The top of the load MISFETs is covered with supply voltage lines so that capacitor elements of a stacked structure are formed between the gate electrodes of the load MISFETs and the supply voltage lines.Type: GrantFiled: May 17, 2001Date of Patent: January 28, 2003Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.Inventors: Shuji Ikeda, Satoshi Meguro, Kyoichiro Asayama, Eri Fujita, Koichiro Ishibashi, Toshiro Aoto, Sadayuki Morita, Atsuyoshi Koike, Masayuki Kojima, Yasuo Kiguchi, Kazuyuki Suko, Fumiyuki Kanai, Naotaka Hashimoto, Toshiaki Yamanaka
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Publication number: 20020160610Abstract: A fabrication method of a semiconductor integrated circuit device including polishing the entire area of an edge of a wafer, for example, by using three polishing drums in which a polishing drum polishes the upper surface of the edge of the water relatively, the polishing drum polishes the central portion of the edge of the wafer relatively and a polishing drum polishes the lower surface of the edge of the wafer relatively, thereby preventing occurrence of obstacles which cause defoliation of thin films on the edge of the wafer.Type: ApplicationFiled: March 1, 2002Publication date: October 31, 2002Inventors: Toshiyuki Arai, Ryousei Kawai, Hirofumi Tsuchiyama, Fumiyuki Kanai, Shinichi Nakabayashi
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Patent number: 6309057Abstract: In an ink-jet type recording head including a nozzle plate provided with nozzle openings, a spacer provided with partitions for partitioning pressure generating chambers, ink supply ports and reservoirs, and a plate member sandwiched and fixed together. Displacement of the plate member is produced by piezoelectric vibrators to thereby generate ink droplets. The spacer is formed by anisotropic etching of a silicon single crystal substrate so that the pressure generating chambers, the ink supply ports and the reservoirs are formed as through-holes communicated with each other. Accordingly, etching conditions for the respective through-holes are made equal to each other. Particularly, through-holes small in sectional area such as the pressure generating chambers and the ink supply ports can be formed with a high accuracy.Type: GrantFiled: January 22, 1999Date of Patent: October 30, 2001Assignee: Seiko Epson CorporationInventors: Atsushi Kobayashi, Tatsuo Furuta, Fumiyuki Kanai, Shinri Sakai, Hiroshi Hosokawa
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Patent number: 6307217Abstract: A static random access memory comprising memory cells each composed of transfer MISFETs controlled by word lines and of a flip-flop circuit made of driver MISFETs and load MISFETs. The top of the load MISFETs is covered with supply voltage lines so that capacitor elements of a stacked structure are formed between the gate electrodes of the load MISFETs and the supply voltage lines.Type: GrantFiled: January 14, 1994Date of Patent: October 23, 2001Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.Inventors: Shuji Ikeda, Satoshi Meguro, Kyoichiro Asayama, Eri Fujita, Koichiro Ishibashi, Toshiro Aoto, Sadayuki Morita, Atsuyoshi Koike, Masayuki Kojima, Yasuo Kiguchi, Kazuyuki Suko, Fumiyuki Kanai, Naotaka Hashimoto, Toshiaki Yamanaka
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Publication number: 20010023965Abstract: A static random access memory comprising memory cells each composed of transfer MISFETs controlled by word lines and of a flip-flop circuit made of driver MISFETs and load MISFETs. The top of the load MISFETs is covered with supply voltage lines so that capacitor elements of a stacked structure are formed between the gate electrodes of the load MISFETs and the supply voltage lines.Type: ApplicationFiled: May 17, 2001Publication date: September 27, 2001Inventors: Shuji Ikeda, Satoshi Meguro, Kyoichiro Asayama, Eri Fujita, Koichiro Ishibashi, Toshiro Aoto, Sadayuki Morita, Atsuyoshi Koike, Masayuki Kojima, Yasuo Kiguchi, Kazuyuki Suko, Fumiyuki Kanai, Naotaka Hashimoto, Toshiaki Yamanaka
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Patent number: 5896150Abstract: In an ink-jet type recording head including a nozzle plate provided with nozzle openings, a spacer provided with partitions for partitioning pressure generating chambers, ink supply ports and reservoirs, and a plate member sandwiched and fixed together. Displacement of the plate member is produced by piezoelectric vibrators to thereby generate ink droplets. The spacer is formed by anisotropic etching of a silicon single crystal substrate so that the pressure generating chambers, the ink supply ports and the reservoirs are formed as through-holes communicated with each other. Accordingly, etching conditions for the respective through-holes are made equal to each other. In different embodiments, the spacer includes chamfered portions or a plurality of fine planes and steps along which adhesive spreads during assembly of the head. In a further embodiment, the spacer includes different length partitions are between the pressure generating chambers.Type: GrantFiled: November 24, 1993Date of Patent: April 20, 1999Assignee: Seiko Epson CorporationInventors: Atsushi Kobayashi, Tatsuo Furuta, Fumiyuki Kanai, Shinri Sakai, Hiroshi Hosokawa
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Patent number: 5880497Abstract: A SRAM having its memory cell constructed to include transfer MISFETs to be controlled by word lines and a flip-flop circuit having driver MISFETs and load MISFETs. Plate electrodes of large area fixed on predetermined power source lines are arranged over the load MISFETs such that the plate electrodes over the offset region of the load MISFETs are formed with an opening. A silicon nitride film having a thickness permeable to hydrogen but not to humidity is formed over the transfer MISFETs and the driver MISFETs formed over the main surface of a semiconductor substrate and the load MISFETs formed of a polycrystalline silicon film deposited on the driver MISFETs.Type: GrantFiled: January 26, 1996Date of Patent: March 9, 1999Assignee: Hitachi, Ltd.Inventors: Shuji Ikeda, Koichi Imato, Kazuo Yoshizaki, Kohji Yamasaki, Soichiro Hashiba, Keiichi Yoshizumi, Yasuko Yoshida, Kousuke Okuyama, Mitsugu Oshima, Kazushi Tomita, Tsuyoshi Tabata, Kazushi Fukuda, Junichi Takano, Toshiaki Yamanaka, Chiemi Hashimoto, Motoko Kawashima, Fumiyuki Kanai, Takashi Hashimoto
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Patent number: 5670409Abstract: A method of fabricating a semiconductor integrated circuit device includes: recessing a second surface portion of a semiconductor substrate; forming elements of a first circuit region capable of performing a first function at a first surface portion of the semiconductor substrate and elements of a second circuit region capable of performing a second function at the recessed second surface portion of the semiconductor substrate, the elements of the first circuit region and those of the second circuit region having relatively small and large sizes as generally measured in a direction perpendicular to the surface portions of the semiconductor substrate, respectively; forming an insulating film to cover the first and second circuit regions, with a result that a level difference is caused between first and second portions of the insulating film on the first and second circuit regions at a relatively lower level and at a relatively higher level, respectively; effecting chemical-mechanical planarization of the insulType: GrantFiled: August 7, 1995Date of Patent: September 23, 1997Assignee: Hitachi, Ltd.Inventors: Hiroshi Otori, Kazuhiko Kajigaya, Kazuyuki Miyazawa, Masaharu Kubo, Atsuyoshi Koike, Fumiyuki Kanai
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Patent number: 5508540Abstract: A SRAM having its memory cell constructed to include transfer MISFETs to be controlled by word lines and a flip-flop circuit having driver MISFETs and load MISFETs. Plate electrodes of large area fixed on predetermined power source lines are arranged over the load MISFETs such that the plate electrodes over the offset region of the load MISFETs are formed with an opening. A silicon nitride film having a thickness permeable to hydrogen but not to humidity is formed over the transfer MISFETs and the driver MISFETs formed over the main surface of a semiconductor substrate and the load MISFETs formed of a polycrystalline silicon film deposited on the driver MISFETs.Type: GrantFiled: February 2, 1994Date of Patent: April 16, 1996Assignee: Hitachi, Ltd.Inventors: Shuji Ikeda, Koichi Imato, Kazuo Yoshizaki, Kohji Yamasaki, Soichiro Hashiba, Keiichi Yoshizumi, Yasuko Yoshida, Kousuke Okuyama, Mitsugu Oshima, Kazushi Tomita, Tsuyoshi Tabata, Kazushi Fukuda, Junichi Takano, Toshiaki Yamanaka, Chiemi Hashimoto, Motoko Kawashima, Fumiyuki Kanai, Takashi Hashimoto