Patents by Inventor Fung-Ching Chao

Fung-Ching Chao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5354701
    Abstract: A process of fabricating a double stacked trench capacitor DRAM cell and resulting DRAM cell is described. The process begins by forming a trench in a semiconductor substrate. A first insulating layer is formed on the top surface of the substrate and on the sidewalls and bottom of the trench. A first contact opening is formed in the first insulating layer. A first polysilicon layer is formed and patterned to overlay the trench surface and a portion on the surface that extends into the contact opening. An insulating layer is formed over the first polysilicon layer. A second polysilicon layer is formed and patterned over the first polysilicon layer. An insulating layer is formed over the second polysilicon layer. A second contact opening is formed in the first insulating layer. A third polysilicon layer is formed over the second polysilicon layer and a portion extending into the second contact opening.
    Type: Grant
    Filed: April 18, 1991
    Date of Patent: October 11, 1994
    Assignee: Industrial Technology Research Institute
    Inventor: Fung-Ching Chao
  • Patent number: 4968640
    Abstract: The invention relates to an improved isolation structure to separate active regions of integrated circuits and a method of its preparation. These isolation structures eliminate the so-called "bird's beak effect" which reduces the effective device area and thereby permit the manufacture of high packing density VLSIs. In the process, a silicon substrate is initially coated, first with a stress-release layer and then with a layer of polysilicon. After the polysilicon is removed from the active device area and patterned, a silicon nitride layer and then a thick layer of photo-resist are coated on the structure. By means of etching, the tops of the polysilicon cusps are exposed. At this stage, the vertical side walls of the polysilicon cusps remain coated with silicon nitride. The polysilicon layer is then completely oxidized to form the field oxide layer. In the final step of the process, the remaining silicon nitride and the stress-release layers are removed.
    Type: Grant
    Filed: December 12, 1988
    Date of Patent: November 6, 1990
    Assignee: Industrial Technology Research Institute
    Inventor: Fung-Ching Chao
  • Patent number: 4906589
    Abstract: A method of fabricating an inverse-T LDDFET with salicide on a substrate is disclosed. The initial steps include anisotropic silicon nitride and incomplete polysilicon etching steps followed by an n.sup.- ion-implantation process. Then oxide sidewall spacers are formed and the unmasked polysilicon is removed completely. The LDDFET structure is formed by the implantation of ions to form heavily-doped source and drain regions. Thereafter oxide sidewall spacers are removed and the thin polysilicon step is oxidized completely. After the silicon nitride and silicon dioxide layers are removed, the self-aligned silicide is applied to form the inverse-T LDDFET with salicide.
    Type: Grant
    Filed: February 6, 1989
    Date of Patent: March 6, 1990
    Assignee: Industrial Technology Research Institute
    Inventor: Fung-Ching Chao
  • Patent number: 4837180
    Abstract: A method of fabricating a lightly-doped drain field effect transistor (LDDFET) is disclosed. The initial steps include anisotropic polysilicon etching and isotropic photoresist erosion to obtain a ladder-shaped polysilicon gate. The polysilicon is partially oxidized and the source/drain region is formed by the implantation of a heavy dose of n-type ions. Thereafter, the silicon dioxide is removed and a lightly doped source/drain region formed by a second ion implantation between the gate region and the heavily doped source/drain region.
    Type: Grant
    Filed: July 9, 1987
    Date of Patent: June 6, 1989
    Assignee: Industrial Technology Research Institute
    Inventor: Fung-Ching Chao
  • Patent number: 4818715
    Abstract: A method of fabricating a lightly-doped drain field effect transistor (LDDFET) with or without self-aligned silicide (salicide) on a substrate is disclosed. The initial steps include either (1) anisotropic silicon nitride and polysilicon etching steps, an isotropic photoresist erosion step, and a second anisotropic etching of part of the silicon nitride to obtain a ladder-shaped polysilicon gate having a silicon nitride thereon; or (2) an anisotropic polysilicon etch step, an isotropic photoresist erosion step to expose part of the unetched polysilicon, and a second anisotropic polysilicon etch step to remove completely the unmasked polysilicon to obtain the ladder-shaped polysilicon gate. The LDD structure is formed by the implantation of ions to form a heavily-doped source and drain regions and lightly-doped regions under the step of the ladder-shaped polysilicon gate layer. Thereafter, the thin polysilicon step is oxidized completely.
    Type: Grant
    Filed: July 9, 1987
    Date of Patent: April 4, 1989
    Assignee: Industrial Technology Research Institute
    Inventor: Fung-Ching Chao
  • Patent number: 4818235
    Abstract: The invention relates to an improved isolation structure to separate active regions of integrated circuits and a method of its preparation. These isolation structures eliminate the so-called "bird's beak effect" which reduces the effective device area and thereby permit the manufacture of high packing desnity VLSIs. In the process, a silicon substrate is initially coated, first with a stress-release layer and then with a layer of polysilicon. After the polysilicon is removed from the active device area and patterned, a silicon nitride layer and then a thick layer of photo-resist are coated on the structure. By means of etching, the tops of the polysilicon cusps are exposed. At this stage, the vertical side walls of the polysilicon cusps remain coated with silicon nitride. The polysilicon layer is then completely oxidized to form the field oxide layer. In the final step of the process, the remaining silicon nitride and the stress-release layers are removed.
    Type: Grant
    Filed: June 7, 1988
    Date of Patent: April 4, 1989
    Assignee: Industry Technology Research Institute
    Inventor: Fung-Ching Chao
  • Patent number: 4755477
    Abstract: A process for defining isolation structures between active regions of an integrated circuit is disclosed. The technique includes first forming a thermally grown silicon dioxide layer. A polysilicon layer is then deposited over the silicon dioxide layer and a silicon nitride-I layer is deposited thereon. A photo-resist mask is then formed on the top of the laminate and selective anisotropic dry etching is used to remove the unmasked silicon nitride-I and polysilicon layers. This step is followed by an isotropic dry etching to undercut the polysilicon beneath the silicon nitride-I layer. After the photo-resist masks and unmasked pad oxide are removed, a layer of silicon nitride-II is deposited. Thereafter, an anisotropic dry etching step is performed to remove the unmasked silicon nitride-II completely. An implantation step is then optionally performed.
    Type: Grant
    Filed: March 24, 1987
    Date of Patent: July 5, 1988
    Assignee: Industrial Technology Research Institute
    Inventor: Fung-Ching Chao