Patents by Inventor Fuqiang Xiao

Fuqiang Xiao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240107804
    Abstract: A display substrate and a display device are provided. The display substrate includes a display region including light emitting units; the light emitting units are arranged into light emitting unit rows, and the light emitting units in one of the light emitting unit rows are arranged along a first direction; the light emitting units include first light emitting units. In at least part of the display region: distances, in the first direction, between a light emitting region of one first light emitting unit and light emitting regions of two of the first light emitting units adjacent to the one first light emitting units are different, and/or distances, in a second direction, between a light emitting region of one first light emitting units and the light emitting regions of two of the first light emitting units adjacent to the one first light emitting units are different.
    Type: Application
    Filed: May 31, 2021
    Publication date: March 28, 2024
    Applicants: Chengdu BOE Optoelectronics Technology Co., Ltd., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Mingwen WANG, Yao HUANG, Xingliang XIAO, Zhong LU, Yuan CHEN, Yamei ZHOU, Yu SONG, Wei HU, Fuqiang LIN
  • Publication number: 20220052002
    Abstract: Systems, methods, and devices for 3D packaging. In some embodiments, a semiconductor package includes a first die and a second die. The first die includes a first bonding pad on a top of the first die and near a first edge of the first die. The second die includes a second bonding pad on a top of the second die and near a second edge of the second die. A pillar is located on the second bonding pad. The first die is mounted on top of the second die such that the first edge is parallel to the second edge and offset from the second edge such that the pillar is exposed. A wire is bonded to a bonding surface of the pillar and bonded to a bonding surface of the first bonding pad.
    Type: Application
    Filed: October 29, 2021
    Publication date: February 17, 2022
    Applicant: Western Digital Technologies, Inc.
    Inventors: Xuyi Yang, Fuqiang Xiao, Cong Zhang, Kuo-Chien Wang, Chin-Tien Chiu
  • Patent number: 11189582
    Abstract: Systems, methods, and devices for 3D packaging. In some embodiments, a semiconductor package includes a first die and a second die. The first die includes a first bonding pad on a top of the first die and near a first edge of the first die. The second die includes a second bonding pad on a top of the second die and near a second edge of the second die. A pillar is located on the second bonding pad. The first die is mounted on top of the second die such that the first edge is parallel to the second edge and offset from the second edge such that the pillar is exposed. A wire is bonded to a bonding surface of the pillar and bonded to a bonding surface of the first bonding pad.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: November 30, 2021
    Assignee: Western Digital Technologies Inc.
    Inventors: Xuyi Yang, Fuqiang Xiao, Cong Zhang, Kuo-Chien Wang, Chin-Tien Chiu
  • Publication number: 20210151399
    Abstract: Systems, methods, and devices for 3D packaging. In some embodiments, a semiconductor package includes a first die and a second die. The first die includes a first bonding pad on a top of the first die and near a first edge of the first die. The second die includes a second bonding pad on a top of the second die and near a second edge of the second die. A pillar is located on the second bonding pad. The first die is mounted on top of the second die such that the first edge is parallel to the second edge and offset from the second edge such that the pillar is exposed. A wire is bonded to a bonding surface of the pillar and bonded to a bonding surface of the first bonding pad.
    Type: Application
    Filed: December 6, 2019
    Publication date: May 20, 2021
    Applicant: Western Digital Technologies, Inc.
    Inventors: Xuyi Yang, Fuqiang Xiao, Cong Zhang, Kuo-Chien Wang, Chin-Tien Chiu
  • Patent number: 10177119
    Abstract: A semiconductor package is disclosed including a number of stacked semiconductor die, electrically connected to each other with wire bonds. The stacked semiconductor die are provided in a mold compound such that a spacing exists between a top die in the die stack and a surface of the mold compound. The wire bonds to the top die may be provided in the spacing. An RDL pad is affixed to the surface of the mold compound. Columns of bumps may be formed on the die bond pads of the top die in the die stack to electrically couple the RDL pad to the die stack across the spacing.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: January 8, 2019
    Assignee: SanDisk Information Technology (Shanghai) Co., Ltd.
    Inventors: Cong Zhang, Fuqiang Xiao, Bin Xu, Haijun Wu, Chin Tien Chiu, Zengyu Zhou
  • Publication number: 20180019228
    Abstract: A semiconductor package is disclosed including a number of stacked semiconductor die, electrically connected to each other with wire bonds. The stacked semiconductor die are provided in a mold compound such that a spacing exists between a top die in the die stack and a surface of the mold compound. The wire bonds to the top die may be provided in the spacing. An RDL pad is affixed to the surface of the mold compound. Columns of bumps may be formed on the die bond pads of the top die in the die stack to electrically couple the RDL pad to the die stack across the spacing.
    Type: Application
    Filed: June 12, 2017
    Publication date: January 18, 2018
    Applicant: SANDISK INFORMATION TECHNOLOGY (SHANGHAI) CO., LTD .
    Inventors: Cong Zhang, Fuqiang Xiao, Bin Xu, Haijun Wu, Chin Tien Chiu, Zengyu Zhou
  • Patent number: 9704797
    Abstract: A wire bonded structure for a semiconductor device is disclosed. The wire bonded structure comprises a bonding pad; and a continuous length of wire mutually diffused with the bonding pad, the wire electrically coupling the bonding pad with a first electrical contact and a second electrical contact different from the first electrical contact.
    Type: Grant
    Filed: May 18, 2011
    Date of Patent: July 11, 2017
    Assignee: SanDisk Information Technology (Shanghai) Co., Ltd.
    Inventors: Zhong Lu, Fen Yu, Chin Tien Chiu, Cheeman Yu, Fuqiang Xiao
  • Publication number: 20140183727
    Abstract: A wire bonded structure for a semiconductor device is disclosed. The wire bonded structure comprises a bonding pad; and a continuous length of wire mutually diffused with the bonding pad, the wire electrically coupling the bonding pad with a first electrical contact and a second electrical contact different from the first electrical contact.
    Type: Application
    Filed: May 18, 2011
    Publication date: July 3, 2014
    Applicants: SANDISK INFORMATION TECHNOLOGY (SHANGHAI) CO., LTD., SANDISK SEMICONDUCTOR (SHANGHAI) CO., LTD.
    Inventors: Zhong Lu, Fen Yu, Chin Tien Chiu, Cheeman Yu, Fuqiang Xiao