Abstract: An interposer including an inner layer structure including at least one inner wiring layer; a first outer layer structure disposed on a first surface of the inner layer structure, the first outer layer structure having rigidity higher than the inner layer structure; and a second outer layer structure disposed on a second surface of the inner layer structure, the second outer layer structure having rigidity higher than the inner layer structure, the inner wiring layer includes wiring disposed on a surface of a first insulating resin layer, which is a photosensitive insulating resin, and a conductive member connected to the wiring and penetrating the first insulating resin layer, the first outer layer structure includes a second insulating resin layer and a conductive member penetrating the second insulating resin layer, the second outer layer structure includes a third insulating resin layer and a conductive member penetrating the third insulating resin layer.

Abstract: A wiring board unit capable of reducing the stress inside the wiring board to reduce the risk of a crack being formed from a location where stress is concentrated. To achieve this, the present invention includes a first wiring board and a second wiring board bonded to the first wiring board. A semiconductor element being resin-sealed on a surface side of the second wiring board opposite to a surface for bonding with the first wiring board. A tensile strength of an insulating resin material used for the second wiring board and a width of a Cu pattern formed on the side opposite to the first wiring board give a value smaller than 0.5 when substituted in Formula 1 below. 1 / ( 1 + Exp ? ( - A ) ) A = - 1 ? 5 .45 - 0.1654 × Tensile ? strength + 11.

Abstract: An electronic component includes a glass base in which through holes are formed passing through both surfaces thereof; an insulating resin layer laminated on each of both surfaces of the glass base and including a copper plated layer formed therein; and a capacitor including a lower electrode formed on the copper plated layer, a dielectric layer laminated on the lower electrode, and an upper electrode laminated on the dielectric layer. In the electronic component, the upper electrode has a region that is parallel to the copper plated layer and is formed so as to be smaller than a region of the dielectric layer parallel to the surface of the copper plated layer or a region of the lower electrode parallel to the surface of the copper plated layer.

Abstract: A semiconductor packaging substrate with a first major surface and a second major surface with an external connection terminal for electrical connection. One or more first wiring layers are on the first major surface side. The first wiring layer includes a first insulating resin layer and a first conductor circuit layer with includes via hole portions and wiring portions. A seed metal layer is formed on three surfaces to which the first insulating resin layer and the wiring portion are grounded, and one or more second wiring layers are formed on the second major surface side. The second wiring layer includes a second insulating resin layer and a second conductor circuit layer of via hole portions and wiring portions, and a seed metal layer is formed on only one surface in which the wiring portion of the second conductor circuit layer and the second insulating resin layer are grounded.

Abstract: An electronic component includes a glass base in which through holes are formed passing through both surfaces thereof; an insulating resin layer laminated on each of both surfaces of the glass base and including a copper plated layer formed therein; and a capacitor including a lower electrode formed on the copper plated layer, a dielectric layer laminated on the lower electrode, and an upper electrode laminated on the dielectric layer. In the electronic component, the upper electrode has a region that is parallel to the copper plated layer and is formed so as to be smaller than a region of the dielectric layer parallel to the surface of the copper plated layer or a region of the lower electrode parallel to the surface of the copper plated layer.

Abstract: A metal photoetching product comprising at least one large cavity of minor axis W1S, major axis W1L and depth D1 in a surface of the product, wherein one or more cavities are included inside at least one of the at least one large cavity, and a smallest hole among the cavities has minor axis of W2S, major axis W2L, and depth D2; and the product satisfies the following dimensions, D1+D2=plate thickness D, 0.02 mm?D?2 mm, 0.4×D<W1S<D, and 0.2×D<W2S<0.8×D.

Abstract: A metal photoetching product comprising at least one large cavity of minor axis W1S, major axis W1L and depth D1 in a surface of the product, wherein one or more cavities are included inside at least one of the at least one large cavity, and a smallest hole among the cavities has minor axis of W2S, major axis W2L, and depth D2; and the product satisfies the following dimensions, D1+D2=plate thickness D, 0.02 mm?D?2 mm, 0.4×D<W1S<D, and 0.2×D<W2S<0.8×D.

Abstract: A metal photoetching product comprising at least one large cavity of minor axis W1S, major axis W1L and depth D1 in a surface of the product, wherein one or more cavities are included inside at least one of the at least one large cavity, and a smallest hole among the cavities has minor axis of W2S, major axis W2L, and depth D2; and the product satisfies the following dimensions, D1+D2=plate thickness D, 0.02 mm?D?2 mm, 0.4×D<W1S<D, and 0.2×D<W2S<0.8×D.

Abstract: A metal photoetching product comprising at least one large cavity of minor axis W1S, major axis W1L and depth D1 in a surface of the product, wherein one or more cavities are included inside at least one of the at least one large cavity, and a smallest hole among the cavities has minor axis of W2S, major axis W2L, and depth D2; and the product satisfies the following dimensions, D1+D2=plate thickness D, 0.02 mm?D?2 mm, 0.4×D<W1S<D, and 0.2×D<W2S<0.8×D.

Abstract: This invention provides a process for producing a printed circuit board characterized by the steps of drilling holes in a copper clad laminate, treating the entire surface of the laminate including the hole-defining inner surfaces with a catalyst, removing the catalyst from the surface of the copper foil of the laminate by mechanically cleaning the surface of the copper foil, depositing electroless nickel only on the hole-defining inner surfaces, forming a pattern with an etching resist, etching away the copper foil except at the pattern area, removing the etching resist, masking with a solder resist the entire surface except at the hole-defining inner surfaces and the lands, and subjecting the hole-defining inner surfaces and the lands to electroless copper plating.