Abstract: An image processing apparatus according to an embodiment of the present disclosure includes processing circuitry. The processing circuitry is configured to obtain volume data of a subject. The processing circuitry is configured to obtain base tubular object data by segmenting the volume data. The processing circuitry is configured to obtain small tubular object data from the volume data. The processing circuitry is configured to generate updated base tubular object data, on the basis of the small tubular object data and the base tubular object data. The processing circuitry is configured to output the updated base tubular object data.

Abstract: A medical image processing apparatus of an embodiment includes processing circuitry. The processing circuitry receives a medical image of a target region. The processing circuitry generates an image pair including a local image having local features of the target region and a global image having global features of the target region on the basis of the received medical image. The processing circuitry performs segmentation and classification of the target region on the image pair by a neural network.

Abstract: A medical image processing apparatus according to an embodiment includes processing circuitry configured: to generate a projection image by implementing an intensity projection on a plurality of two-dimensional images structuring three-dimensional volume data rendering a tubular organ; to obtain a mapping matrix of the intensity projection; to annotate the tubular organ in the projection image; and to identify the tubular organ in the three-dimensional volume data, by inversely mapping the tubular organ annotated in the projection image onto the three-dimensional volume data while using the mapping matrix.

Abstract: Aspects of the present disclosure include a dual path phase locked loop (PLL) circuit with a switched capacitor filter topology along with systems, method, devices, and other circuits related thereto. The dual path PLL circuit includes an integral path and a proportional path. Both the integral path and proportional path include a charge pump and a loop filter. The outputs of a phase frequency detector (PFD) are sent to both charge pumps. The output of the integral path charge pump is connected to a capacitor, and the voltage on capacitor is used as the integral path control voltage for a voltage-controlled oscillator (VCO). A switched capacitor network is connected to the output of the proportional path charge pump and used to generate the proportional path control voltage for the VCO. Together, the two control voltages dictate the VCO's output frequency.

Abstract: Aspects of the present disclosure include systems, methods, devices, and circuits for fast settling of a bias node. Consistent with some embodiments, a bias circuit may include a successive-approximation-register-analog-to-digital converter (SAR-ADC) based settling loop configured to perform a fast settling process for a heavily loaded bias node. The SAR-ADC based loop performs a SAR-ADC process that includes measuring a reference signal to determine a number of cells in a capacitor array that are involved in a charge sharing process while simultaneously completing the settling process for the bias node.

Abstract: Aspects of the present disclosure include a frequency-to-current (F2I) circuit and systems, methods, devices, and other circuits related thereto. The F2I circuit is implemented with a delta-modulator-based control loop to settle and maintain an operating point on a bias node. The control loop provides an integral of an output of a comparator, and the comparator compares it to a self-built voltage reference. Upon powering on the circuit, an integrator in the control loop starts to integrate the charge on both a bias voltage and an internal voltage to provide a settling process for the internal voltage to approximate the reference voltage and for the bias voltage to approximate a predetermined operating point of the bias node. After the circuit has settled, the comparator's output charge toggles and the internal voltage and bias voltage become sawtooth-like waveforms at the reference voltage and operating points, respectively.