Patents by Inventor Fwu-Juh Huang

Fwu-Juh Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of packing-based macro placement and semiconductor chip using the same
    Patent number: 8661388
    Abstract: A multi-packing tree (MPT) macro placer. The MPT macro placer comprises reading input files in a LEF/DEF format, creating a k-level binary multi-packing tree comprising k branch nodes each corresponding to one level and k+1 packing sub-trees each corresponding to one of the nodes and comprising a group of macros, optimizing the multi-packing tree according to a packing result thereof, and generating output files in a DEF format.
    Type: Grant
    Filed: October 1, 2009
    Date of Patent: February 25, 2014
    Assignee: Mediatek Inc.
    Inventors: Tung-Chieh Chen, Ping-Hung Yu, Yao-Wen Chang, Fwu-Juh Huang, Tien-Yueh Liu
  • CHIP WITH ESD PROTECTION FUNCTION
    Publication number: 20110242712
    Abstract: An exemplary chip includes an input/output (I/O) area and a core area is provided. The input/output (I/O) area has a first I/O block operated under a first power domain and a second I/O block operated under a second power domain placed therein, wherein a voltage range of the first power domain is distinct from a voltage range of the second power domain. The core area has at least one circuit therein performing at least one function of the chip, and the core area further has at least one power cut cell placed therein wherein the power cut cell is coupled to the first I/O block and the second I/O block via a plurality of connectors for providing an electrostatic discharge (ESD) path between the first I/O block and the second I/O block.
    Type: Application
    Filed: April 1, 2010
    Publication date: October 6, 2011
    Inventors: Fwu-Juh Huang, Bo-Shih Huang
  • METHOD OF PACKING-BASED MACRO PLACEMENT AND SEMICONDUCTOR CHIP USING THE SAME
    Publication number: 20100023910
    Abstract: A multi-packing tree (MPT) macro placer. The MPT macro placer comprises reading input files in a LEF/DEF format, creating a k-level binary multi-packing tree comprising k branch nodes each corresponding to one level and k+1 packing sub-trees each corresponding to one of the nodes and comprising a group of macros, optimizing the multi-packing tree according to a packing result thereof, and generating output files in a DEF format.
    Type: Application
    Filed: October 1, 2009
    Publication date: January 28, 2010
    Applicant: MEDIATEK INC.
    Inventors: Tung-Chieh Chen, Ping-Hung Yu, Yao-Wen Chang, Fwu-Juh Huang, Tien-Yueh Liu
  • METHOD OF PACKING-BASED MACRO PLACEMENT AND SEMICONDUCTOR CHIP USING THE SAME
    Publication number: 20070157146
    Abstract: A multi-packing tree (MPT) macro placer. The MPT macro placer comprises reading input files in a LEF/DEF format, creating a k-level binary multi-packing tree comprising k branch nodes each corresponding to one level and k+1 packing sub-trees each corresponding to one of the nodes and comprising a group of macros, optimizing the multi-packing tree according to a packing result thereof, and generating output files in a DEF format.
    Type: Application
    Filed: December 8, 2006
    Publication date: July 5, 2007
    Applicant: MEDIATEK INC.
    Inventors: Tung-Chieh Chen, Ping-Hung Yu, Yao-Wen Chang, Fwu-Juh Huang, Tien-Yueh Liu