Abstract: A method for operating an apparatus that includes a program memory, a data memory and a status register that holds a status, wherein the status has fields including: a program memory address at which a most recent instruction is fetched from the program memory, a data memory access address at which data has most recently been accessed in the data memory by the apparatus and a repeat count indicating a number of times an operation specified in a current program instruction remains to be performed, the apparatus further including a condition register having condition fields corresponding to the status fields held in the status register, the method including: writing the condition register with a condition including the condition fields; and generating an interrupt request to a processing core in response to detecting that the status held in the status register satisfies the condition specified in the condition register.

Abstract: A programmable apparatus includes a program memory that holds instructions of a program fetched and executed by the apparatus, a data memory that holds data processed by the instructions, a status register that holds a status having fields: a program memory address at which a most recent instruction is fetched from the program memory, a data memory access address at which data has most recently been accessed in the data memory by the apparatus and a repeat count that indicates a number of times an operation specified in a current program instruction remains to be performed. A condition register has condition fields corresponding to the status register fields. Control logic generates an interrupt request to a processing core in response to detecting that the status held in the status register satisfies the condition specified in the condition register.

Abstract: An apparatus includes a first memory, processing units that access the first memory, and a counter that, for each period of a sequence of periods, holds an indication of accesses to the first memory during the period; and control logic that, for each period of the sequence of periods, monitors the indication to determine whether it exceeds the threshold and, if so, stalls the processing units from accessing the first memory for a remaining portion of the period.

Abstract: An apparatus including first and second reservation stations. The first reservation station dispatches a load micro instruction, and indicates on a hold bus if the load micro instruction is a specified load micro instruction directed to retrieve an operand from a prescribed resource other than on-core cache memory. The second reservation station is coupled to the hold bus, and dispatches one or more younger micro instructions therein that depend on the load micro instruction for execution after a number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus that the load micro instruction is the specified load micro instruction, the second reservation station is configured to stall dispatch of the one or more younger micro instructions until the load micro instruction has retrieved the operand.

Abstract: A first data storage holds cache lines, an accelerator has a second data storage that selectively holds accelerator data and cache lines evicted from the first data storage, a tag directory holds tags for cache lines stored in the first and second data storages, and a mode indicator indicates whether the second data storage is operating in a first or second mode in which it respectively holds cache lines evicted from the first data storage or accelerator data. In response to a request to evict a cache line from the first data storage, in the first mode the control logic writes the cache line to the second data storage and updates a tag in the tag directory to indicate the cache line is present in the second data storage, and in the second mode the control logic instead writes the cache line to a system memory.

Abstract: An apparatus is provided for protecting a basic input/output system (BIOS) in a computing system. The apparatus includes a BIOS read only memory (ROM), an event detector, and a tamper detector. The BIOS ROM has BIOS contents that are stored as plaintext, and an encrypted message digest, where the encrypted message digest comprises an encrypted version of a first message digest that corresponds to the BIOS contents, and where and the encrypted version is generated via a symmetric key algorithm and a key. The event detector is configured to generate a BIOS check interrupt that interrupts normal operation of the computing system upon the occurrence of an event, where the event includes one or more occurrences of a power glitch exceeding a specified threshold within a specified time period.

Abstract: An apparatus is provided for protecting a basic input/output system (BIOS) in a computing system. The apparatus includes a BIOS read only memory (ROM), an event detector, and a tamper detector. The BIOS ROM has BIOS contents that are stored as plaintext, and an encrypted message digest, where the encrypted message digest comprises an encrypted version of a first message digest that corresponds to the BIOS contents, and where and the encrypted version is generated via a symmetric key algorithm and a key. The event detector is configured to generate a BIOS check interrupt that interrupts normal operation of the computing system upon the occurrence of an event, where the event includes one or more occurrences of a fuse array access.

Abstract: A hardware processing unit is provided. The hardware processing unit includes: an accumulator; a multiplier-adder receives first and second factors and receives an addend, the multiplier-adder generates a sum of the addend and a product of the first and second factors and provides the sum; a first multiplexer receives a first operand, a positive one, and a negative one and selects one of them for provision as the first factor to the multiplier-adder; a second multiplexer receives a second operand, a positive one, and a negative one and selects one of them for provision as the second factor to the multiplier-adder; a third multiplexer, having an output, that receives the first operand and the second operand and selects one of them for provision on its output; and a fourth multiplexer receives the third multiplexer output and the sum and selects one of them for provision to the accumulator.

Abstract: A hardware data compressor includes a first hardware engine that scans an input block of characters to produce a stream of tokens, the stream of tokens comprising replacement back pointers to matched strings of characters of the input block and non-replaced characters of the input block. The hardware data compressor also includes a second hardware engine that receives the stream of tokens and maintains a sorted list of symbols associated with the tokens. The hardware data compressor also includes the second hardware engine concurrently maintains the sorted list of symbols by frequency of occurrence as the first hardware engine produces the tokens of the stream.

Abstract: A microprocessor includes a plurality of dynamically reconfigurable functional units, a fingerprint, and a fingerprint unit. As the plurality of dynamically reconfigurable functional units execute instructions according to a first configuration setting, the fingerprint unit accumulates information about the instructions according to a mathematical operation to generate a result. The microprocessor also includes a reconfiguration unit that reconfigures the plurality of dynamically reconfigurable functional units to execute instructions according to a second configuration setting in response to an indication that the result matches the fingerprint.

Abstract: First/second memories hold rows of N weight/data words. The first memory address has log2W bits and an extra bit. Each of N processing units (PU) of index J has first and second registers, an accumulator, an arithmetic unit performs an operation thereon to accumulate a result, first multiplexing logic for PUs 0 through (N/2)?1 receives first memory weight words J and J+(N/2) and for PUs N/2 through N?1 receives first memory weight words J and J?(N/2) and outputs a selected weight word to the first register, and second multiplexing logic receives second memory data word J and data word output by the second register of PU J?1 and outputs a selected data word to the second register. PU 0 second multiplexing logic also receives PU (N/2)?1 second register data word, and PU N/2 second multiplexing logic also receives PU N?1 second register data word.

Abstract: First/second memories hold rows of N weight/data words. Each of N processing units (PU) of index J have a register, an accumulator having an output, an arithmetic unit that performs an operation thereon to accumulate a result, the first input receives the output of the accumulator, the second input receives a respective first memory weight word, the third input receives a respective data word output by the register, and multiplexing logic receives a respective second memory data word and a data word output by the register of PU J?1 and outputs a selected data word to the register. PU J?1 for PU 0 is PU N?1. The multiplexing logic of PU 0 also receives the data word output by the register of PU (N/2)?1. The multiplexing logic of PU N/2 also receives the data word output by the register of PU N?1.

Abstract: First/second memories hold rows of N weight/data words. Each of N processing units (PU) of index J have a register, an accumulator having an output, an arithmetic unit that performs an operation thereon to accumulate a result, the first input receives the output of the accumulator, the second input receives a respective first memory weight word, the third input receives a respective data word output by the register, and multiplexing logic receives a respective second memory data word and a data word output by the register of PU J?1 and outputs a selected data word to the register. PU J?1 for PU 0 is PU N?1. The multiplexing logic of PU N/4 also receives the data word output by the register of PU (3N/4)?1. The multiplexing logic of PU 3N/4 also receives the data word output by the register of PU (N/4)?1.

Abstract: A memory holds D rows of N words and receives an address having log2D bits and an extra bit. Each of N processing units (PU) of index J has first and second registers, an accumulator, an arithmetic unit that performs an operation thereon to accumulate a result, and multiplexing logic receiving memory word J, and for PUs 0 to (N/2)?1 also memory word J+(N/2). In a first mode, the multiplexing logic of PUs 0 to N?1 selects word J to output to the first register. In a second mode: when the extra bit is a zero, the multiplexing logic of PUs 0 to (N/2)?1 selects word J to output to the first register, and when the extra bit is a one, the multiplexing logic of PUs 0 through (N/2)?1 selects word J+(N/2) to output to the first register.

Abstract: In a neural network unit, each neural processing unit (NPU) of an array of N NPUs receives respective first and second upper and lower bytes of 2N bytes received from first and second RAMs. In a first mode, each NPU sign-extends the first upper byte to form a first 16-bit word and performs an arithmetic operation on the first 16-bit word and a second 16-bit word formed by the second upper and lower bytes. In a second mode, each NPU sign-extends the first lower byte to form a third 16-bit word and performs the arithmetic operation on the third 16-bit word and the second 16-bit word formed by the second upper and lower bytes. In a third mode, each NPU performs the arithmetic operation on a fourth 16-bit word formed by the first upper and lower bytes and the second 16-bit word formed by the second upper and lower bytes.

Abstract: A processor comprises a neural network unit (NNU) and a processing complex (PC) comprising a processing core and cache memory. The NNU comprises neural processing units (NPU), cache control logic (CCL) and a memory array (MA). To transition from a first mode in which the MA operates to hold neural network weights for the array of NPUs to a second mode in which the MA and CCL operate as a victim cache, the CCL begins to cache evicted cache lines into the MA in response to eviction requests and begins to provide to the PC lines that hit in the MA in response to load requests. To transition from the second mode to the first mode, the CCL invalidates all lines of the MA, ceases to cache evicted lines into the MA in response to eviction requests, and ceases to provide to the PC lines in response to load requests.

Abstract: N processing units (PU) each have an arithmetic unit (AU) that performs an operation on first, second and third inputs to generate a result to store in an accumulator having an output provided to the first input. A weight input is received by the AU second input. A multiplexed register has first, second, third and fourth data inputs and an output received by the third AU input. A first memory provides N weight words to the N weight inputs. A second memory provides N data words to the multiplexed register first data inputs. The multiplexed register output is also received by the second, third, and fourth data input of the multiplexed register one, 2?J, and 2?K PUs away, respectively. The N multiplexed registers collectively operate as an N-word rotater that rotates by one, 2?J, or 2?K words when the control input specifies the second, third, or fourth data input, respectively.

Abstract: A processor comprising a mode indicator, a plurality of processing cores, and a neural network unit (NNU), comprising a memory array, an array of neural processing units (NPU), cache control logic, and selection logic that selectively couples the plurality of NPUs and the cache control logic to the memory array. When the mode indicator indicates a first mode, the selection logic enables the plurality of NPUs to read neural network weights from the memory array to perform computations using the weights. When the mode indicator indicates a second mode, the selection logic enables the plurality of processing cores to access the memory array through the cache control logic as a cache memory.

Abstract: A neural network unit convolves a H×W×C input with F R×S×C filters to generate F Q×P outputs. N processing units (PU) each have a register receiving a memory word and a multiplexed-register selectively receiving a memory word or word rotated from an adjacent PU multiplexed-register. The N PUs are logically partitioned as G blocks each of B PUs. The PUs convolve in a column-channel-row order. For each filter column: the N registers read a memory row, each PU multiplies the register and the multiplexed-register to generate a product to accumulate, and the multiplexed-registers are rotated by one; the multiplexed-registers are rotated to align the input blocks with the adjacent PU block. This is performed for each channel. For each filter row, N multiplexed-registers read a memory row for the multiply-accumulations, F column-channel-row-sums are generated and written to the memory, then all steps are performed for each output row.

Abstract: A processor comprising a plurality of processing cores, a last level cache memory (LLC) shared by the plurality of processing cores, and a neural network unit (NNU) comprising an array of neural processing units (NPU) and a memory array. The LLC comprises a plurality of slices. To transition from a first mode in which the memory array operates to store neural network weights read by the plurality of NPUs to a second mode in which the memory array operates as a slice of the LLC in addition to the plurality of slices, the processor write-back-invalidates the LLC and updates a hashing algorithm to include the memory array as a slice of the LLC in addition to the plurality of slices. To transition from the second mode to the first mode, the processor write-back-invalidates the LLC and updates the hashing algorithm to exclude the memory array from the LLC.