Patents by Inventor G. Krishna Kumar

G. Krishna Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200084242
    Abstract: Embodiments are directed to systems and methods configured to detect malware vulnerabilities in computational environments. The method includes receiving input data distributed among a plurality of nodes within a particular network, receiving the input data into a curator engine to convert the at least one input data into a payload having at least one message header, receiving the payload having the at least one message header into a transaction engine, and storing the payload having the at least one message header into a blockchain database. The method continues by processing the payload having the at least one message header to make a decision to transform or analyze the transaction based on a predetermined set of rules, converting the payload into a data file, evaluating the data file, aggregating the data file for a plurality of behavior models, and converting the data file into a valid message payload with a header.
    Type: Application
    Filed: November 18, 2019
    Publication date: March 12, 2020
    Inventors: Rakesh Babu Katragadda, Juan Ramirez, G. Krishna Kumar, Chandana Karipineni, Saritha Vellanki, Sudha Kolachalam
  • Patent number: 10542046
    Abstract: Embodiments are directed to systems and methods configured to gather, transmit, share and process security related data between end users and security applications/devices across multiple platforms using blockchain open implementation as the backend and smart contracts integrated with artificial intelligence and behavior analysis using rule engines to enforce/implement data decisions. The system is designed to continuously predict, monitor, prevent, detect, response and mitigate cyber threats. The process includes a self-enforced adaptable engine that has a fast incident response time and makes quick smart decisions. This is a resilient system that is constantly capturing data, learning, tracking and enforcing. Computational power is maximized by leveraging smart contracts to validate transactions between network devices, share encrypted and protected information about their functions, events across the network of nodes and make smart swarm decisions.
    Type: Grant
    Filed: September 13, 2018
    Date of Patent: January 21, 2020
    Assignee: Unifyvault LLC
    Inventors: Rakesh Babu Katragadda, Juan Ramirez, G. Krishna Kumar, Chandana Karipineni, Saritha Vellanki, Sudha Kolachalam
  • Publication number: 20190379699
    Abstract: Embodiments are directed to systems and methods configured to gather, transmit, share and process security related data between end users and security applications/devices across multiple platforms using blockchain open implementation as the backend and smart contracts integrated with artificial intelligence and behavior analysis using rule engines to enforce/implement data decisions. The system is designed to continuously predict, monitor, prevent, detect, response and mitigate cyber threats. The process includes a self-enforced adaptable engine that has a fast incident response time and makes quick smart decisions. This is a resilient system that is constantly capturing data, learning, tracking and enforcing. Computational power is maximized by leveraging smart contracts to validate transactions between network devices, share encrypted and protected information about their functions, events across the network of nodes and make smart swarm decisions.
    Type: Application
    Filed: September 13, 2018
    Publication date: December 12, 2019
    Inventors: Rakesh Babu Katragadda, Juan Ramirez, G. Krishna Kumar, Chandana Karipineni, Saritha Vellanki, Sudha Kolachalam
  • Patent number: 8101469
    Abstract: A method of forming Monolithic CMOS-MEMS hybrid integrated, packaged structures includes the steps of providing: providing at least one semiconductor substrate having a CMOS device area including dielectric layers and metallization layers; applying at least one protective layer overlying the CMOS device area; forming at least one opening on the protective layer and patterning the dielectric and metallization layers to access the semiconductor substrate; forming at least one opening on the semiconductor substrate by etching the dielectric and metallization layers; applying at least one filler layer in the at least one opening on the semiconductor substrate; positioning at least one chip on the filler layer, the chip including a prefabricated front face and a bare backside; applying a first insulating layer covering the front face of the chip providing continuity from the semiconductor substrate to the chip; forming at least one via opening on the insulating layer covering the chip to access at least one contac
    Type: Grant
    Filed: March 26, 2010
    Date of Patent: January 24, 2012
    Assignee: Advanced Microfab, LLC
    Inventors: G. Krishna Kumar, Nishit A. Choksi, Joseph M. Chalil
  • Patent number: 8101458
    Abstract: A method of forming Monolithic CMOS-MEMS hybrid integrated, packaged structures includes the steps of providing: providing a semiconductor substrate with pre-fabricated cmos circuits on the front side and a polished back-side with through substrate conductive vias; forming at least one opening in the polished backside of the semiconductor substrate by appropriately protecting the front-side; applying at least one filler material in the at least one opening on the semiconductor substrate; positioning at least one prefabricated mems, nems or cmos chip on the filler material, the chip including a front face and a bare back face with the prefabricated mems/nems chips containing mechanical and dielectric layers; applying at least one planarization layer overlying the substrate, filler material and the chip; forming at least one via opening on a portion of the planarization layer interfacing pads on the chip and the through substrate conductive vias; applying at least one metallization layer overlying the planariza
    Type: Grant
    Filed: August 12, 2010
    Date of Patent: January 24, 2012
    Assignee: Advanced Microfab, LLC
    Inventors: G. Krishna Kumar, Nishit A. Choksi, Joseph M. Chalil
  • Patent number: 7989248
    Abstract: A method of forming Monolithic CMOS-MEMS hybrid integrated, packaged structures includes the steps of providing: providing at least one semiconductor substrate having a CMOS device area including dielectric layers and metallization layers; applying at least one protective layer overlying the CMOS device area; forming at least one opening on the protective layer and patterning the dielectric and metallization layers to access the semiconductor substrate; forming at least one opening on the semiconductor substrate by etching the dielectric and metallization layers; applying at least one filler layer in the at least one opening on the semiconductor substrate; positioning at least one chip on the filler layer, the chip including a prefabricated front face and a bare backside; applying a first insulating layer covering the front face of the chip providing continuity from the semiconductor substrate to the chip; forming at least one via opening on the insulating layer covering the chip to access at least one contac
    Type: Grant
    Filed: July 2, 2009
    Date of Patent: August 2, 2011
    Assignee: Advanced Microfab, LLC
    Inventors: G. Krishna Kumar, Nishit A. Choksi, Joseph M. Chalil
  • Publication number: 20110054579
    Abstract: A flexible penetrating array for neuronal applications includes an insulating layer. A conductive layer is formed on the insulating layer. A flexible polymer substrate is formed on the conductive layer; the polymer substrate includes defined penetrating electrodes. A first metallization layer is formed on the polymer substrate. A second flexible polymer layer is formed on the first metallization layer. A second metallization layer is formed on the second flexible polymer layer. A third flexible polymer layer is formed on the second metallization layer. The third flexible polymer layer is patterned to expose the second metallization layer that is integrated with the out of plane conductive layer and first metallization layer. Also disclosed is a method of forming the array.
    Type: Application
    Filed: August 25, 2009
    Publication date: March 3, 2011
    Applicant: Advanced Microfab, LLC
    Inventors: G. Krishna Kumar, Joseph M. Chalil, Nishit A. Choksi
  • Publication number: 20110027941
    Abstract: A method of forming Monolithic CMOS-MEMS hybrid integrated, packaged structures includes the steps of providing: providing a semiconductor substrate with pre-fabricated cmos circuits on the front side and a polished back-side with through substrate conductive vias; forming at least one opening in the polished backside of the semiconductor substrate by appropriately protecting the front-side; applying at least one filler material in the at least one opening on the semiconductor substrate; positioning at least one prefabricated mems, nems or cmos chip on the filler material, the chip including a front face and a bare back face with the prefabricated mems/nems chips containing mechanical and dielectric layers; applying at least one planarization layer overlying the substrate, filler material and the chip; forming at least one via opening on a portion of the planarization layer interfacing pads on the chip and the through substrate conductive vias; applying at least one metallization layer overlying the planariza
    Type: Application
    Filed: August 12, 2010
    Publication date: February 3, 2011
    Applicant: Advanced Microfab, LLC
    Inventors: G. Krishna Kumar, Nishit A. Choksi, Joseph M. Chalil
  • Publication number: 20110003422
    Abstract: A method of forming Monolithic CMOS-MEMS hybrid integrated, packaged structures includes the steps of providing: providing at least one semiconductor substrate having a CMOS device area including dielectric layers and metallization layers; applying at least one protective layer overlying the CMOS device area; forming at least one opening on the protective layer and patterning the dielectric and metallization layers to access the semiconductor substrate; forming at least one opening on the semiconductor substrate by etching the dielectric and metallization layers; applying at least one filler layer in the at least one opening on the semiconductor substrate; positioning at least one chip on the filler layer, the chip including a prefabricated front face and a bare backside; applying a first insulating layer covering the front face of the chip providing continuity from the semiconductor substrate to the chip; forming at least one via opening on the insulating layer covering the chip to access at least one contac
    Type: Application
    Filed: July 2, 2009
    Publication date: January 6, 2011
    Applicant: Advanced Microfab, LLC
    Inventors: Rakesh Katragadda, G. Krishna Kumar, Nishit A. Choksi, Joseph M. Chalil
  • Publication number: 20110003421
    Abstract: A method of forming Monolithic CMOS-MEMS hybrid integrated, packaged structures includes the steps of providing: providing at least one semiconductor substrate having a CMOS device area including dielectric layers and metallization layers; applying at least one protective layer overlying the CMOS device area; forming at least one opening on the protective layer and patterning the dielectric and metallization layers to access the semiconductor substrate; forming at least one opening on the semiconductor substrate by etching the dielectric and metallization layers; applying at least one filler layer in the at least one opening on the semiconductor substrate; positioning at least one chip on the filler layer, the chip including a prefabricated front face and a bare backside; applying a first insulating layer covering the front face of the chip providing continuity from the semiconductor substrate to the chip; forming at least one via opening on the insulating layer covering the chip to access at least one contac
    Type: Application
    Filed: March 26, 2010
    Publication date: January 6, 2011
    Applicant: Advanced Microfab, LLC
    Inventors: G. Krishna Kumar, Nishit A. Choksi, Joseph M. Chalil