Abstract: An on-chip split transaction system bus having separate address and data portions is provided. The system bus contains separate address and data buses for initiating and tracking out-of-order transactions on either or both of the address or data portions of the bus. The system bus provides communication via a bus interface that includes split transaction tracking and control to establish transaction ID's for each transaction initiated by the bus interface, and to determine whether data appearing on the data portion of the system bus is associated with one of its pending transactions. The bus interface also contains flow control logic to determine whether devices that are to be read from, or written to, by the bus interface, have resources (buffers) available to respond to the transactions. If the resources are available, the flow control logic allows the transactions to proceed, and adjusts its counters to reflect the use of the resources.

Abstract: An apparatus is presented for improving the efficiency of data transfers between devices interconnected over an on-chip system bus a multi-master computer system configuration. Bus efficiency is improved by providing an apparatus for controlling a read-modify-write transaction to an address in a bus slave device that does not suspend essential features of the system bus during the transaction, namely, pipelining and transaction splitting. The apparatus includes transaction control logic in a bus master device and transaction response logic in a bus slave device. The transaction control logic provides a write barrier command from the bus master device over the on-chip system bus to the bus slave device. The transaction response logic receives the write barrier command, and precludes execution of future transactions to the address within the bus slave device until completion of the read-modify-write transaction while allowing execution of transactions to other addresses within the bus slave device to complete.

Abstract: A macropipelined microprocessor chip adheres to strict read and write ordering by sequentially buffering operands in queues during instruction decode, then removing the operands in order during instruction execution. Any instruction that requires additional access to memory inserts the requests into the queued sequence (in a specifier queue) such that read and write ordering is preserved. A specifier queue synchronization counter captures synchronization points to coordinate memory request operations among the autonomous instruction decode unit, instruction execution unit, and memory sub-system. The synchronization method does not restrict the benefit of overlapped execution in the pipelined. Another feature is treatment of a variable bit field operand type that does not restrict the location of operand data. Instruction execution flows in a pipelined processor having such an operand type are vastly different depending on whether operand data resides in registers or memory.

Abstract: An operation of a processor is traced while fetching instructions from a memory to operate the processor. The tracing involves detecting an unpredictable fetching of instructions on the assumption that a predictable fetching can be reconstructed without any further input. The unpredictable fetching is identified as being due to either computable, conditional, or unanticipated events. Upon detecting the events, process control information, such as the next instruction to be fetched is recorded in a queue, and from the queue the information can be stored in a trace buffer. During reconstruction of the operation, the trace buffer, and the image including the instructions can be examined to analyze the real-time operation of the processor.

Abstract: A data flow of a processor is traced while accessing data stored in a memory and in a plurality of registers during operation of the processor. The tracing involves detecting an unpredictable accessing of data on the assumption that a predictable accessing can be reconstructed without any further input. The unpredictable accessing is identified by setting and clearing a trace bit associated with each of the registers according to identifying the accessing as direct memory-to-register, register-to-register, constant-to-register, and indirect memory. If a trace bit is set on a register storing data being used as a base address during the indirect memory acceding, data flow control information, such as the base address stored in the register being used during the indirect acceding is recorded in a queue, and from the queue the information can be stored in a trace buffer.

Abstract: Multi-processor systems are often implemented using a common system bus as the communication mechanism between CPU, memory, and I/O adapters. It is also common to include features on each CPU module, such as cache memory, that enhance the performance of the execution of instructions in the CPU. Many architectures require that the hardware employ a mechanism by which the data in the individual CPU cache memories is kept consistent with data in main memory and with data in other cache memories. One such method involves each CPU monitoring transactions on the system bus, and taking appropriate action when a transaction appears on the bus which would render data in the CPU's cache incoherent. If the CPU uses queues to hold records of incoming transaction information until it can service them, the bus interface must guarantee that the queued items are processed by the cache in the correct order. If this is not done, certain types of shared data protocols fail to operate correctly.

Abstract: A macropipelined microprocessor chip adheres to strict read and write ordering by sequentially buffering operands in queues during instruction decode, then removing the operands in order during instruction execution. Any instruction that requires additional access to memory inserts the requests into the queued sequence (in a specifier queue) such that read and write ordering is preserved. A specifier queue synchronization counter captures synchronization points to coordinate memory request operations among the autonomous instruction decode unit, instruction execution unit, and memory sub-system. The synchronization method does not restrict the benefit of overlapped execution in the pipelined. Another feature is treatment of a variable bit field operand type that does not restrict the location of operand data. Instruction execution flows in a pipelined processor having such an operand type are vastly different depending on whether operand data resides in registers or memory.

Abstract: A pipelined CPU executing instructions of variable length, and referencing memory using various data widths. Macroinstruction pipelining is employed (instead of microinstruction pipelining), with queuing between units of the CPU to allow flexibility in instruction execution times. A wide bandwidth is available for memory access; fetching 64-bit data blocks on each cycle. Internal processor registers are accessed with short (byte width) addresses instead of full physical addresses as used for memory and I/O references, but off-chip processor registers are memory-mapped and accessed by the same busses using the same controls as the memory and I/O.

Abstract: A system for evaluating the performance of a computer system having a processor that passes through a plurality of processor states during operation and an associated system memory includes an operating unit for receiving a request to monitor specific process states from a user. Firmware causes the processor to enter the desired processor state requested by the user. The hardware identifies the occurrence of the desired processor state. Information relating to the occurrence of the desired process state is accumulated the memory. The accumulated information is read from memory and a report is provided to the user.

Abstract: To reduce the processing time required for correcting a fault, the instruction decorder segment and the first execution segment of a pipelined processor are provided with "state silos" that are operative during normal instruction execution to save a sufficient amount of state information to immediately restart the instruction decoder segment and the first execution segment by reloading the state information having been stored in the state silos. The state silos, for example, include a queue of registers clocked by a common clocking signal that is inhibited during correction of the fault. When the fault is corrected, multiplexers select the state information from the silos to be used by the respective pipeline segments. In a preferred embodiment, the instruction decoder segment decodes variable length macroinstructions into operand specifiers and operations to perform upon the specifiers.

Abstract: An apparatus which filters the number of invalidates to be propagated onto a private processor bus is provided. This is desirable so that the processor bus is not overloaded with invalidate requests. The present invention describes a method of filtering the number of invalidates to be propagated to each processor. A memory interface filters the invalidates by using a second private bus, the invalidate bus, which communicates with the cache controller. The cache controller can tell the memory interface whether data corresponding to the address on the invalidate bus is resident in the private cache memory of that processor. In this way, the memory interface only has to request the private processor bus when necessary, in order to perform the invalidate.

Abstract: A processor for use in a digital data processing system including a main memory and a write buffer for buffering write data and associated addresses from the processor for storage in the storage locations identified by the associated addresses in the main memory. In response to selection occurances, such as a context switch, which cannot be detected outside of the processor, the processor asserts a signal which enables the write buffer to transfer all of its contents to the main memory. The write buffer, in turn, disables the processor while it is transferring data to the main memory.