Abstract: Methods and apparatus for providing an assembly including a base substrate, a lid substrate, and a ring frame between the base substrate and the lid substrate to define a protected volume, where the ring frame includes through vias. A die may be contained in the protected volume. Sensor circuitry can include conductive pillars in the protected volume and the die can include circuity to determine an impedance of the pad and the pillars for tamper detection. An edge cap can be coupled to at least one side of the assembly for tamper detection.

Abstract: Methods and apparatus for providing an assembly including a base substrate, a lid substrate, and a ring frame between the base substrate and the lid substrate to define a protected volume, where the ring frame includes through vias. A die may be contained in the protected volume. Sensor circuitry can include conductive pillars in the protected volume and the die can include circuity to determine an impedance of the pad and the pillars for tamper detection. An edge cap can be coupled to at least one side of the assembly for tamper detection.

Abstract: Structures and methods of fabricating semiconductor wafer assemblies that encapsulate one or die in a cavity etched into an oxide bonded semiconductor wafer stack. The methods generally include the steps of positioning the die in the cavity, mechanically and electrically mounting the die to the wafer stack, and encapsulating the die within the cavity by bonding a lid wafer to the wafer stack in one of multiple ways. Semiconductor processing steps are applied to construct the assemblies (e.g., deposition, annealing, chemical and mechanical polishing, etching, etc.) and connecting the die (e.g., bump bonding, wire interconnecting, ultrasonic bonding, oxide bonding, etc.) according to the embodiments described above.

Abstract: In one aspect, a unit cell of a phased array antenna includes a metal plate having a hole, a first side and a second side opposite the first side, a first plurality of laminate layers disposed on the first side, a second plurality of layers disposed on the second side of the metal plate, a radiator disposed in the first plurality of layer on the first side, a feed circuit disposed in the second plurality of laminate layers on the second side and configured to provide excitation signals to the radiator and a first plurality of vias extending through the hole connecting the feed circuit to the radiator.

Abstract: In one aspect, an active electronically scanned array (AESA) tile includes a radiator structure and oxide-bonded semiconductor wafers attached to the radiator structure and comprising a radio frequency (RF) manifold and a beam former. An RF signal path through the oxide-bonded wafers comprises a first portion that propagates toward the beam former and a second portion that propagates parallel to the beam former.

Abstract: A heat dissipation structure for a semiconductor integrated circuit die having a plurality of connection areas may include a thermal mount comprising a plurality of pillars each having an aspect ratio preferable greater than 2:1 and each positioned to connect to one of the connection areas on a peripheral portion of the semiconductor integrated circuit die with one of a plurality of interface layers. A thermal conductivity of materials for the connection areas, the thermal mount, the pillars, each of which is preferably copper, and the interface layers, which are preferably copper nanoparticle layers, has a thermal conductivity greater than 100 Watts per meter degree Kelvin (W/m·K). Flexure of the pillars accommodates mechanical strain arising from temperature changes and differences in coefficients of thermal expansion for materials of the semiconductor integrated circuit die and the thermal mount.

Abstract: A heat dissipation structure for a semiconductor integrated circuit die having a plurality of connection areas may include a thermal mount comprising a plurality of pillars each having an aspect ratio preferable greater than 2:1 and each positioned to connect to one of the connection areas on a peripheral portion of the semiconductor integrated circuit die with one of a plurality of interface layers. A thermal conductivity of materials for the connection areas, the thermal mount, the pillars, each of which is preferably copper, and the interface layers, which are preferably copper nanoparticle layers, has a thermal conductivity greater than 100 Watts per meter degree Kelvin (W/m·K). Flexure of the pillars accommodates mechanical strain arising from temperature changes and differences in coefficients of thermal expansion for materials of the semiconductor integrated circuit die and the thermal mount.

Abstract: Structures and methods of fabricating semiconductor wafer assemblies that encapsulate one or die in a cavity etched into an oxide bonded semiconductor wafer stack. The methods generally include the steps of positioning the die in the cavity, mechanically and electrically mounting the die to the wafer stack, and encapsulating the die within the cavity by bonding a lid wafer to the wafer stack in one of multiple ways. Semiconductor processing steps are applied to construct the assemblies (e.g., deposition, annealing, chemical and mechanical polishing, etching, etc.) and connecting the die (e.g., bump bonding, wire interconnecting, ultrasonic bonding, oxide bonding, etc.) according to the embodiments described above.

Abstract: Structures and methods of fabricating semiconductor wafer assemblies that encapsulate one or die in a cavity etched into an oxide bonded semiconductor wafer stack. The methods generally include the steps of positioning the die in the cavity, mechanically and electrically mounting the die to the wafer stack, and encapsulating the die within the cavity by bonding a lid wafer to the wafer stack in one of multiple ways. Semiconductor processing steps are applied to construct the assemblies (e.g., deposition, annealing, chemical and mechanical polishing, etching, etc.) and connecting the die (e.g., bump bonding, wire interconnecting, ultrasonic bonding, oxide bonding, etc.) according to the embodiments described above.

Abstract: Structures and methods of fabricating semiconductor wafer assemblies that encapsulate one or die in a cavity etched into an oxide bonded semiconductor wafer stack. The methods generally include the steps of positioning the die in the cavity, mechanically and electrically mounting the die to the wafer stack, and encapsulating the die within the cavity by bonding a lid wafer to the wafer stack in one of multiple ways. Semiconductor processing steps are applied to construct the assemblies (e.g., deposition, annealing, chemical and mechanical polishing, etching, etc.) and connecting the die (e.g., bump bonding, wire interconnecting, ultrasonic bonding, oxide bonding, etc.) according to the embodiments described above.

Abstract: In one aspect, a unit cell of a phased array antenna includes a metal plate having a hole, a first side and a second side opposite the first side, a first plurality of laminate layers disposed on the first side, a second plurality of layers disposed on the second side of the metal plate, a radiator disposed in the first plurality of layer on the first side, a feed circuit disposed in the second plurality of laminate layers on the second side and configured to provide excitation signals to the radiator and a first plurality of vias extending through the hole connecting the feed circuit to the radiator.

Abstract: In one aspect, an active electronically scanned array (AESA) tile includes a radiator structure and oxide-bonded semiconductor wafers attached to the radiator structure and comprising a radio frequency (RF) manifold and a beam former. An RF signal path through the oxide-bonded wafers comprises a first portion that propagates toward the beam former and a second portion that propagates parallel to the beam former.

Abstract: A heat-dissipating device includes at least one heat-dissipating surface and a micro-sized cooling mechanism formed directly on the heat-dissipating surface by an additive manufacturing process. The cooling mechanism includes at least one fluid passage, such as a micro-hose, for carrying a cooling medium from a coolant source directly to the heat-dissipating surface. The cooling mechanism is fluidly sealed to the heat-dissipating surface such that the cooling medium is in thermal contact directly with the heat-dissipating surface.

Abstract: A coincident phased dual-polarized antenna array configured to emit electromagnetic radiation includes: a plurality of electromagnetic radiators arranged in a grid, the plurality of electromagnetic radiators defining a plurality of notches; a ground plane spaced from the electromagnetic radiators; a conductive layer disposed between the electromagnetic radiators and the ground plane, the conductive layer having a plurality of slots laterally offset from the notches and being spaced apart from and electrically insulated from the electromagnetic radiators; and a plurality of feeds, each of the feeds spanning a corresponding slot of the slots and electrically connected to a portion of the conductive layer at one side of the corresponding slot.

Abstract: A coolant distribution structure for an MMIC having: an input/output layer with an input port for receiving a coolant for transmission to coolant channels in the MMIC and an output port for exiting the coolant after such coolant has cooled active devices in the MMIC, a coolant pass-through layer to receive the coolant from the input port and having structure to inhibit such received coolant from passing directly to the output port, a coolant distribution layer for receiving coolant passing from the coolant pass-through layer and distributing such received coolant to the cooling channels to absorb heat generated by the active devices and then directing heated coolant to the coolant distribution layer and out of the porting layer via the passthrough layer. The coolant pass-through layer has a structure configured to inhibit such heated coolant from passing directly to the input port prior to such heated absorbed coolant being transmitted to the output port.

Abstract: A heat-dissipating device includes at least one heat-dissipating surface and a micro-sized cooling mechanism formed directly on the heat-dissipating surface by an additive manufacturing process. The cooling mechanism includes at least one fluid passage, such as a micro-hose, for carrying a cooling medium from a coolant source directly to the heat-dissipating surface. The cooling mechanism is fluidly sealed to the heat-dissipating surface such that the cooling medium is in thermal contact directly with the heat-dissipating surface.

Abstract: A coolant distribution structure for an MMIC having: an input/output layer with an input port for receiving a coolant for transmission to coolant channels in the MMIC and an output port for exiting the coolant after such coolant has cooled active devices in the MMIC, a coolant pass-through layer to receive the coolant from the input port and having structure to inhibit such received coolant from passing directly to the output port, a coolant distribution layer for receiving coolant passing from the coolant pass-through layer and distributing such received coolant to the cooling channels to absorb heat generated by the active devices and then directing heated coolant to the coolant distribution layer and out of the porting layer via the pass-through layer. The coolant pass-through layer has a structure configured to inhibit such heated coolant from passing directly to the input port prior to such heated absorbed coolant being transmitted to the output port.

Abstract: A flip-chip mounted semiconductor structure having a flip chip mounting pad and a circuit structure flip-chip mounted to the flip chip mounting pad. The circuit structure includes: a semiconductor die; and a stiffener structure attached to the die, the stiffener structure having a conduit passing through the stiffener structure between a front side of the stiffener structure and a hack side of the stiffener structure, the stiffener and attached die having a degree of rigidity greater than the die alone.

Abstract: A circuit board assembly includes a circuit board, a chip attached to the circuit board and a dielectric layer. The chip has a circuit facing the circuit board and spaced from it. The dielectric layer includes an aerogel. In one embodiment, the aerogel has a dielectric constant of approximately 2.0 or less and a compression strength of at least approximately 100 psi.

Abstract: A coincident phased dual-polarized antenna array configured to emit electromagnetic radiation includes: a plurality of electromagnetic radiators arranged in a grid, the plurality of electromagnetic radiators defining a plurality of notches; a ground plane spaced from the electromagnetic radiators; a conductive layer disposed between the electromagnetic radiators and the ground plane, the conductive layer having a plurality of slots laterally offset from the notches and being spaced apart from and electrically insulated from the electromagnetic radiators; and a plurality of feeds, each of the feeds spanning a corresponding slot of the slots and electrically connected to a portion of the conductive layer at one side of the corresponding slot.