Abstract: Ganaka is a computer which operates using models as operands, and is suitable for big data and machine learning applications. This invention describes how succinct descriptions of data based on convex hulls, and approximations thereof, can be derived, and how efficiently computations can be performed taking into account extreme variability in resource needs. A variety of architectural optimizations is described.

Abstract: A method and apparatus are disclosed for terminating optical links in an opticalnetwork based on performance requirements. The present invention forces the termination of the received optical signals at each node only on the protection ring and does not force termination on the working ring, unless necessary to satisfy performance requirements. A signal on an end-to-end light path on the working ring is terminated only when required by engineering rules, such as signal-to-noise requirements. Specifically, the present invention does not force terminate an end-to-end light path on the working ring at a given node (or on a link between two nodes) unless the signal will fail to meet certain criteria, such as a minimum optical signal-to-noise ratio, at the next node.

Abstract: A communications service is provided for packet networks such as the Internet (herein termed “fuzzycast” service ) which provides statistical assurance that, on the average, all destinations get some percentage of offered traffic. The switch, at a router or ATM node, services a fuzzycast message by estimating the congestion on the route specified by the IP protocol header. The switch is free to temporarily drop those destinations whose routes are congested, as determined, for example, from the length of the outgoing queue. For each fuzzycast message, a subset K of the M destinations is chosen, advantageously by using a random number generator, and the message is sent to the chosen destinations, if possible.

Abstract: A receiver for signals generated using a modulation scheme such as quadrature-phase shift-keying (QPSK) modulation. The receiver characterizes the variance in the detected signal constellation and, when appropriate, adjusts at least some part of its processing in order to reduce power consumption or error rate. For example, when the variance is low and full receiver operation is not required to achieve accurate phase detection, one or more of the following changes are made to reduce power consumption: the resolution of the A/D converter is reduced, the precision of digital filtering is reduced, and/or one or more of the digital filters are turned off. If the variance in the detected signal constellation should increase, appropriate changes may be made to gradually restore the operations of the full receiver as needed to reduce error rate. In this way, the receiver can efficiently regulate its power consumption without jeopardizing the accuracy of its signal processing.

Abstract: The invention concerns an arbitration scheme for permitting access to the bus of a computer. The arbitration scheme has the ability to control and reduce the delay experienced by any device by monitoring the queue length of the device and using information concerning the device, such as device rate, phase, data transfer size and queue length. Specifically, the arbiter prevents periodic accessing devices, such as audio and video samplers, from being delayed or interrupted for long periods of time once they have begun accessing the bus.

Abstract: A codec which normally provides impedance synthesis, filtering, suppression of receive signal echoes, and gain equalization for a plurality of line circuits under the control of a microprocessor includes an arrangement for ascertaining the actual impedance of each line that it serves and making a corresponding adjustment of the receive and transmit equalizers and other codec parameters. A series of short tones having precisely known amplitude frequencies throughout the voice band are applied to the line when the line is on-hook and during the off-hook interval before tone is returned to the subscriber. Impedance is measured by observing the echo and obtaining an estimate of the phase by performing a least squares fit during a time interval not exceeding the usual interdigital call signaling interval.

Abstract: A unique cache structure with some addressing flexibility and a unique linker method that generates program code with a minimized WCET and takes advantage of the flexibility of the cache structure is provided. The method generates relocatable object modules for each function of the program code. Suitable starting locations for theses objects modules are generated and linked together forming an executable version of the program code. WCET analysis is performed on the executable code. The WCET is then compared to the previous best WCET estimate. The starting locations of the modules providing the better WCET are stored as the best configuration for the program code. The process may be repeated until the WCET is suitably minimized. The unique cache structure allows the WCET minimized program code to reside contiguously in memory, while being properly cached according to the results of the linker method.

Abstract: A user-programmable bass/treble control circuit is embedded within a conventional remotely located codec. A subscriber station set is capable of transmitting out-of-voiceband “control” tones to increase/decrease bass and treble. A tone detector within the codec recognizes and removes these control tones, forwarding them to a programmable equalization filter inserted in the transmit signal path in the codec. The equalization filter will adjust the bass and treble of the to-be-transmitted signal in accordance with these received control tones. Advantageously, the “listener” at the other end will not hear the tones if the tone detector is inserted before the receiver. The user may adjust the tones during the entire conversation and the filter may be “reset” at call completion.

Abstract: An adaptive interference canceller employing digital synthesis techniques and a digital to analog converter for eliminating narrow band RFI.

Abstract: A simple high speed Real-Time method and apparatus for processing a queue in a network queue server is presented. Long packets at the beginning of the queue are processed while a pointer chains down the queue to find shorter packets. When a shorter packet is found the pointer stops and waits for a timing threshold to be met. When the timing threshold is met the short packet is processed until completion and then work is resumed on the long packet. The method is implemented using a pointer to identify the position in the queue that is currently being processed, a pointer to search for the shorter packets, two registers to hold values of the respective pointers and memory to hold the location of the discontinued packet. An additional register is utilized to hold the incremented cycle processing time, and a final register is used to hold a threshold value for processing a packet. Lastly, a previous pseudo head register is also utilized when the queue is not doubly linked.

Abstract: An arrangement for reducing power consumption in a flash A/D converter uses a predictor module to compute the "next" digital output value (i.e., s(n+1)) and then uses this value to regulate the number of individual comparators required to perform an accurate conversion. The predictor module is disposed as a feedback element between the converter output and the comparator array. Based upon the prediction, the module transmits a control signal to the comparator array, turning "on" and "off" subsets of the comparators forming the array. By maintaining a large number of the comparators in the "off" state (usually, only half of the comparators need to be enabled), a significant power savings can be realized.

Abstract: A receiver for input signals generated using a phase-based modulation scheme such as bipolar-phase shift-keying (BPSK) modulation or quadrature-phase shift-keying (QPSK) modulation. The receiver can sample the input signal using one of at least two different sampling frequencies that are selected such that at least one of the sampling frequencies is not harmonically related to the carrier frequency of the input signal by a ratio of small numbers. In this way, the receiver can avoid interference patterns that can result when the sampling frequency and the carrier frequency are harmonically related. In one embodiment, the receivers are hard-limiting receivers that are suitable for use in the remote nodes of fiber-to-the-curb (FTTC) communication systems, where low-power receivers are desirable.

Abstract: In accordance with the principles of the invention, a multiprocessor scheduling and execution system and method is disclosed for signal processing tasks on P processors using a computer to schedule the execution. The method comprises representing the signal processing tasks in a manner stored within the computer so as to determine flow equations and timing constraints for the processor scheduling, performing corrected gradient descents on the stored representation of the signal processing tasks using the determined timing constraints and an error criterion until substantial convergence to a processor schedule occurs, and executing the signal processing tasks on the P processors substantially in accordance with the processor schedule.