Abstract: An analog-to-digital converter (ADC) (112) for sampling high speed video signals includes Pre-amplifiers (502, 504, 506) electrically coupled to Post-amplifiers (508, 510, 512) that are electrically coupled to output latches (514, 517, 519, 521, 523, 525, and 527). A sampling clock signal (116) clocks the output latches (514, 517, 519, 521, 523, 525, and 527) to sample an input analog electronic signal to provide a digital representation thereof. The ADC (112) includes an auto-zeroing function to cancel bias voltages at the Post-amplifiers (508, 510, 512) during a video signal horizontal blanking time period. The ADC (112) includes a bit dithering function by alternating sets of reference voltages into the Pre-amplifiers (502, 504, 506) increasing bit resolution. The ADC (112) includes wired interconnect interpolation between the Pre-amplifiers (502, 504, 506) and Post-amplifiers (508, 510, 512) and between the Post-amplifiers (508, 510, 512) and the output latches (514, 517, 519, 521, 523, 525, and 527).

Abstract: An analog-to-digital converter (500) for sampling high speed video signals includes a first input (502) for receiving an electronic signal, a sampling clock input (547) for receiving a sampling clock signal, and first and second sampling circuits. The first sampling circuit is arranged in a differential circuit arrangement, and is electrically connected to the first input (502) and to the sampling clock input (547) and is responsive to the sampling clock signal, for sampling the electronic signal to provide a pair of boundary reference voltage signals (706, 708, 710, 712) that bound the voltage of the sampled electronic signal, and further to convert the sampled electronic signal to provide the most significant bits (554) of a digital representation of the electronic signal at times indicated by the sampling clock signal.