Abstract: A signal generator including a DDS-signal source that is configured to operate according to the principle of direct digital synthesis (DDS), and a PLL signal synthesizer that is configured to operate according to the principle of phase locked loop (PLL) using an output signal from the DDS-signal source as a reference signal. The DDS-signal source can be connected via a direct connection, without further frequency division or mixing, directly to an output of the signal generator or directly to a level-adjustment device of the signal generator in order to generate a portion of an overall frequency range of an output signal of the signal generator.

Abstract: A signal generator including a DDS-signal source that is configured to operate according to the principle of direct digital synthesis (DDS), and a PLL signal synthesizer that is configured to operate according to the principle of phase locked loop (PLL) using an output signal from the DDS-signal source as a reference signal. The DDS-signal source can be connected via a direct connection, without further frequency division or mixing, directly to an output of the signal generator or directly to a level-adjustment device of the signal generator in order to generate a portion of an overall frequency range of an output signal of the signal generator.

Abstract: A frequency synthesizer according to the direct digital synthesis method is provided. The frequency synthesizer includes a phase accumulator for the cyclical incrementation of a phase signal by a phase increment M present at the input of the phase accumulator, a memory unit with a table of sine-function values stored in its memory cells for the determination of sine-function values corresponding to phase values of the phase signal, a digital-to-analog converter for the conversion of time-discrete sine-function values into a quasi-analog sinusoidal time function and an anti-aliasing low-pass filter for smoothing the quasi-analog sinusoidal time function. The frequency synthesizer additionally contains an adder, which is connected between the memory unit and the digital-to-analog converter and which superimposes a non-periodic signal over the time-discrete sine-function values.