Abstract: An apparatus for storing data in a nonvolatile memory includes a controller configured to erase a group of physical memory cells in the nonvolatile memory. The controller is configured to write multiple bits of information to each of a first group of physical memory cells in the nonvolatile memory. The controller is configured to map a logical address range to a physical address range for the first group of physical memory cells in the nonvolatile memory. The controller is configured to determine if the first group of physical memory cells fails a data integrity test. If the first group of physical memory cells fails the data integrity test, the controller writes at least some of the information stored in the first group of physical memory cells to a second group of physical memory cells in the nonvolatile memory. The controller writes a single bit of information per cell in the second group of physical memory cells.

Abstract: An apparatus for storing data in a nonvolatile memory includes a controller configured to erase a group of physical memory cells in the nonvolatile memory. The controller is configured to write multiple bits of information to each of a first group of physical memory cells in the nonvolatile memory. The controller is configured to map a logical address range to a physical address range for the first group of physical memory cells in the nonvolatile memory. The controller is configured to determine if the first group of physical memory cells fails a data integrity test. If the first group of physical memory cells fails the data integrity test, the controller writes at least some of the information stored in the first group of physical memory cells to a second group of physical memory cells in the nonvolatile memory. The controller writes a single bit of information per cell in the second group of physical memory cells.

Abstract: An apparatus for storing data in a nonvolatile memory includes a controller configured to erase a group of physical memory cells in the nonvolatile memory. The controller is configured to write multiple bits of information to each of a first group of physical memory cells in the nonvolatile memory. The controller is configured to map a logical address range to a physical address range for the first group of physical memory cells in the nonvolatile memory. The controller is configured to determine if the first group of physical memory cells fails a data integrity test. If the first group of physical memory cells fails the data integrity test, the controller writes at least some of the information stored in the first group of physical memory cells to a second group of physical memory cells in the nonvolatile memory. The controller writes a single bit of information per cell in the second group of physical memory cells.

Abstract: A flash controller for managing at least one MLC non-volatile memory module and at least one SLC non-volatile memory module. The flash controller is adapted to determine if a range of addresses listed by an entry and mapped to said at least one MLC non-volatile memory module fails a data integrity test. In the event of such a failure, the controller remaps said entry to an equivalent range of addresses of said at least one SLC non-volatile memory module. The flash controller is further adapted to determine which of the blocks in the MLC and SLC non-volatile memory modules are accessed most frequently and allocating those blocks that receive frequent writes to the SLC non-volatile memory module and those blocks that receive infrequent writes to the MLC non-volatile memory module.

Abstract: A controller for managing at least one MLC non-volatile memory space including at least one MLC non-volatile memory element and at least one SLC non-volatile memory space including at least one SLC non-volatile memory element. The controller is adapted to determine if a range of addresses listed by an entry and mapped to the at least one MLC non-volatile memory element fails a data integrity test performed at the controller based upon received data retained at the controller and which received data is stored in the at least one MLC memory element as stored data. In the event of such a failure, the controller remaps said entry to an the at least one SLC non-volatile memory element.

Abstract: A controller for managing at least one MLC non-volatile memory space including at least one MLC non-volatile memory element and at least one SLC non-volatile memory space including at least one SLC non-volatile memory element. The controller is adapted to determine if a range of addresses listed by an entry and mapped to the at least one MLC non-volatile memory element fails a data integrity test performed at the controller based upon received data retained at the controller and which received data is stored in the at least one MLC memory element as stored data. In the event of such a failure, the controller remaps said entry to an the at least one SLC non-volatile memory element.

Abstract: A flash controller for managing at least one MLC non-volatile memory module and at least one SLC non-volatile memory module. The flash controller is adapted to determine if a range of addresses listed by an entry and mapped to said at least one MLC nonvolatile memory module fails a data integrity test. In the event of such a failure, the controller remaps said entry to an equivalent range of addresses of said at least one SLC non-volatile memory module. The flash controller is further adapted to determine which of the blocks in the MIX and SLC nonvolatile memory modules are accessed most frequently and allocating those blocks that receive frequent writes to the SLC non-volatile memory module and those blocks that receive infrequent writes to the MLC non-volatile memory module.

Abstract: A method for storing data comprises maintaining an address table for a memory space containing volatile memory and nonvolatile memory space. The nonvolatile memory space includes both multi-level cell (MLC) space and single level cell (SLC) space and the volatile memory includes a random access volatile memory element. An address table maps logical and physical addresses adaptable to the system by the address table. The mapping is performed as necessitated by the system to maximize lifetime maps data in at least one of volatile or nonvolatile memories. Storing received data within a controller memory associated with the at least one controller. Controlling access of the MLC and SLC nonvolatile memory elements and the random access volatile memory element for storage of the received data.

Abstract: A flash controller for managing at least one MLC non-volatile memory module and at least one SLC non-volatile memory module. The flash controller is adapted to determine if a range of addresses listed by an entry and mapped to said at least one MLC non-volatile memory module fails a data integrity test. In the event of such a failure, the controller remaps said entry to an equivalent range of addresses of said at least one SLC non-volatile memory module. The flash controller is further adapted to determine which of the blocks in the MLC and SLC non-volatile memory modules are accessed most frequently and allocating those blocks that receive frequent writes to the SLC non-volatile memory module and those blocks that receive infrequent writes to the MLC non-volatile memory module.

Abstract: Exemplary apparatus includes a nonvolatile memory, a volatile memory separate from the nonvolatile memory, and a controller configured to access the volatile memory and the nonvolatile memory. Exemplary volatile memory is configured to function as a read/write cache. The controller may be configured to perform a read/modify/write memory operation that involves both the volatile memory and the nonvolatile memory. Exemplary devices may have a host interface and may include a data connection configured to perform double data rate data transfer. Exemplary volatile memory may support byte-granularity memory read operations, and the density of the volatile memory may be substantially less than the density of the nonvolatile memory.

Abstract: Most semiconductor devices manufactured today, have uniform dopant concentration, either in the lateral or vertical device active (and isolation) regions. By grading the dopant concentration, the performance in various semiconductor devices can be significantly improved. Performance improvements can be obtained in application specific areas like increase in frequency of operation for digital logic, various power MOSFET and IGBT ICs, improvement in refresh time for DRAMs, decrease in programming time for nonvolatile memory, better visual quality including pixel resolution and color sensitivity for imaging ICs, better sensitivity for varactors in tunable filters, higher drive capabilities for iFETs, and a host of other applications.

Abstract: A flash controller for managing at least one MLC non-volatile memory module and at least one SLC non-volatile memory module. The flash controller is adapted to determine if a range of addresses listed by an entry and mapped to said at least one MLC non-volatile memory module fails a data integrity test. In the event of such a failure, the controller remaps said entry to an equivalent range of addresses of said at least one SLC non-volatile memory module. The flash controller is further adapted to determine which of the blocks in the MLC and SLC non-volatile memory modules are accessed most frequently and allocating those blocks that receive frequent writes to the SLC non-volatile memory module and those blocks that receive infrequent writes to the MLC non-volatile memory module.

Abstract: Most semiconductor devices manufactured today, have uniform dopant concentration, either in the lateral or vertical device active (and isolation) regions. By grading the dopant concentration, the performance in various semiconductor devices can be significantly improved. Performance improvements can be obtained in application specific areas like increase in frequency of operation for digital logic, various power MOSFET and IGBT ICs, improvement in refresh time for DRAMs, decrease in programming time for nonvolatile memory, better visual quality including pixel resolution and color sensitivity for imaging ICs, better sensitivity for varactors in tunable filters, higher drive capabilities for JFETs, and a host of other applications.

Abstract: A controller for managing at least one MLC non-volatile memory module and at least one SLC non-volatile memory module. The flash controller is adapted to determine if a range of addresses listed by an entry and mapped to said at least one MLC non-volatile memory module fails a data integrity test. In the event of such a failure, the controller remaps said entry to an equivalent range of addresses of said at least one SLC non-volatile memory module. The flash controller is further adapted to determine which of the blocks in the MLC and SLC non-volatile memory modules are accessed most frequently and allocating those blocks that receive frequent writes to the SLC non-volatile memory module and those blocks that receive infrequent writes to the MLC non-volatile memory module.

Abstract: A nonvolatile memory system is described with novel architecture coupling nonvolatile storage memory with random access volatile memory. New commands are included to enhance the read and write performance of the memory system.

Abstract: Most semiconductor devices manufactured today, have uniform dopant concentration, either in the lateral or vertical device active (and isolation) regions. By grading the dopant concentration, the performance in various semiconductor devices can be significantly improved. Performance improvements can be obtained in application specific areas like increase in frequency of operation for digital logic, various power MOSFET and IGBT ICS, improvement in refresh time for DRAM's, decrease in programming time for nonvolatile memory, better visual quality including pixel resolution and color sensitivity for imaging ICs, better sensitivity for varactors in tunable filters, higher drive capabilities for JFET's, and a host of other applications.

Abstract: A nonvolatile memory system is described with novel architecture coupling nonvolatile storage memory with random access volatile memory. New commands are included to enhance the read and write performance of the memory system.

Abstract: A flash controller for managing at least one MLC non-volatile memory module and at least one SLC non-volatile memory module. The flash controller is adapted to determine if a range of addresses listed by an entry and mapped to said at least one MLC non-volatile memory module fails a data integrity test. In the event of such a failure, the controller remaps said entry to an equivalent range of addresses of said at least one SLC non-volatile memory module, The flash controller is farther adapted to determine which of the blocks in the MLC and SLC non-volatile memory modules are accessed most frequently and allocating those blocks that receive frequent writes to the SLC non-volatile memory module and those blocks that receive infrequent writes to the MLC non-volatile memory module.

Abstract: Most semiconductor devices manufactured today, have uniform dopant concentration, either in the lateral or vertical device active (and isolation) regions. By grading the dopant concentration, the performance in various semiconductor devices can be significantly improved. Performance improvements can be obtained in application specific areas like increase in frequency of operation for digital logic, various power MOSFET and IGBT ICS, improvement in refresh time for DRAM's, decrease in programming time for nonvolatile memory, better visual quality including pixel resolution and color sensitivity for imaging ICs, better sensitivity for varactors in tunable filters, higher drive capabilities for JFET's, and a host of other applications.

Abstract: A nonvolatile memory system is described with novel architecture coupling nonvolatile storage memory with random access volatile memory. New commands are included to enhance the read and write performance of the memory system.