Abstract: A method of controllably aligning carbon nanotubes to a template structure to fabricate a variety of carbon nanotube containing structures and devices having desired characteristics is provided. The method allows simultaneous, selective growth of both vertically and horizontally controllably aligned nanotubes on the template structure but not on a substrate in a single process step.

Abstract: An electrical device is disclosed. The electrical device includes a substrate, and a self-assembled molecular layer on the substrate. The self-assembled molecular layer comprises a plurality of molecules, each molecule comprising a first end proximate to the substrate and a second end comprising sulfur distal to the substrate. A copper layer is on the self-assembled molecular layer.

Abstract: The present invention provides a method for forming a diffusion barrier layer, a diffusion barrier in an integrated circuit and an integrated circuit. The method for forming a diffusion barrier involves the following steps: 1) preparing a silicon substrate; 2) contacting the silicon substrate with a composition comprising self-assembled monolayer subunits and a solvent; and, 3) removing the solvent. The diffusion barrier layer includes a self-assembled monolayer. The integrated circuit includes a silicon substrate, a diffusion barrier layer and a metal deposited on the diffusion barrier layer. The diffusion barrier layer in the integrated circuit is covalently attached to the silicon substrate and includes a self-assembled monolayer.

Abstract: A method of controllably aligning carbon nanotubes to a template structure to fabricate a variety of carbon nanotube containing structures and devices having desired characteristics is provided. The method allows simultaneous, selective growth of both vertically and horizontally controllably aligned nanotubes on the template structure but not on a substrate in a single process step.

Abstract: The present invention provides a diffusion barrier in an integrated circuit. The diffusion barrier comprises a self-assembled monolayer. The diffusion barrier is preferably less than 5 nm thick; more preferably it is less than 2 nm thick. The self-assembled monolayer typically contains an aromatic group at its terminus.

Abstract: The present invention provides a method for forming a diffusion barrier layer, a diffusion barrier in an integrated circuit and an integrated circuit. The method for forming a diffusion barrier involves the following steps: 1) preparing a silicon substrate; 2) contacting the silicon substrate with a composition comprising self-assembled monolayer subunits and a solvent; and, 3) removing the solvent. The diffusion barrier layer includes a self-assembled monolayer. The integrated circuit includes a silicon substrate, a diffusion barrier layer and a metal deposited on the diffusion barrier layer. The diffusion barrier layer in the integrated circuit is covalently attached to the silicon substrate and includes a self-assembled monolayer.