Abstract: The invention relates to a pharmaceutical formulation, e.g. a paediatric formulation, of odevixibat, which comprises a plurality of small particles. The formulation may be used in the treatment of liver diseases such as bile acid-dependent liver diseases, and particularly cholestatic liver diseases such as biliary atresia, progressive familial intrahepatic cholestasis (PFIC), Alagille syndrome (ALGS) and paediatric cholestatic pruritus. The invention also relates to a process for the preparation of the pharmaceutical formulation.

Abstract: The invention relates to a pharmaceutical formulation, e.g. a paediatric formulation, of odevixibat, which comprises a plurality of small particles. The formulation may be used in the treatment of liver diseases such as bile acid-dependent liver diseases, and particularly cholestatic liver diseases such as biliary atresia, progressive familial intrahepatic cholestasis (PFIC), Alagille syndrome (ALGS) and paediatric cholestatic pruritus. The invention also relates to a process for the preparation of the pharmaceutical formulation.

Abstract: A method is provided by a central-unit-control plane (CU-CP) of a network node for exchanging information with a central-unit user plane (CU-UP) of the network node to manage Quality of Service (QoS) flows for the optimization of radio resources. The method includes transmitting, to the CU-UP, a request for flow information for at least one QoS flow and receiving, from the CU-UP of the network node, the flow information for the at least one QoS flow. Based on the flow information for the at least one QoS flow, at least one action is taken.

Abstract: There is provided a display device, which is arranged to display a predetermined fixed image, having a pixel electrode layer comprising a plurality of pixel portions, and opaque solidified electrolyte arranged in a plurality of separated segments in ionic contact with a respective pixel portion, wherein each electrolyte segment and respective pixel portion form a pixel element. The fixed image display further comprises at least one continuous electrode layer extending across at least two rows and two columns of the pixel matrix, and is connected to the electrolyte segments of a subset of the pixel elements. Upon application of an electric potential difference between the patterned electrode layer and the pixel electrode layer, the pixel portions of the subset of the pixel elements switch color.

Abstract: There is provided a display device, which is arranged to display a predetermined fixed image, having a pixel electrode layer comprising a plurality of pixel portions, and opaque solidified electrolyte arranged in a plurality of separated segments in ionic contact with a respective pixel portion, wherein each electrolyte segment and respective pixel portion form a pixel element. The fixed image display further comprises at least one continuous electrode layer extending across at least two rows and two columns of the pixel matrix, and is connected to the electrolyte segments of a subset of the pixel elements. Upon application of an electric potential difference between the patterned electrode layer and the pixel electrode layer, the pixel portions of the subset of the pixel elements switch color.

Abstract: A moisture sensor, for measuring moisture in a building without leaving visible scars to the building surface, is provided. The moisture sensor includes a flexible carrier carrying an antenna for receiving EM-radiation between 9 kHz and 11 MHz and a resonant circuit including a moisture reactive element. The moisture reactive element includes a hygroscopic electrolyte arranged between a first and a second electrode, wherein the electrolyte in the presence of moisture forms mobile ions and provides a complex impedance at least in response to the alternating voltage, which complex impedance varies with the moisture content of the electrolyte.

Abstract: In a non-volatile electric memory system a memory unit and a read/write unit are provided as physically separate units. The memory unit is based on a memory material that can be set to at least two distinct physical states by applying an electric field across the memory material. Electrodes and/or contacts are either provided in the memory unit or in the read/write unit and contacts are at least always provided in the read/write unit. Electrodes and contacts are provided in a geometrical arrangement, which defines geometrically one or more memory cells in the memory layer. Establishing a physical contact between the memory unit and the read/write unit closes an electrical circuit over the addressed memory cell such that read, write or erase operations can be effected. The memory material of the memory unit can be polarized into two discernible polarization states.

Abstract: A moister sensor, for measuring moister in a building without leaving visible scars to the building surface, is provided. The moister sensor includes a flexible carrier carrying an antenna for receiving EM-radiation between 9 kHz and 11 MHz and a resonant circuit including a moister reactive element. The moister reactive element includes a hygroscopic electrolyte arranged between a first and a second electrode, wherein the electrolyte in the presence of moister forms mobile ions and provides a complex impedance at least in response to the alternating voltage, which complex impedance varies with the moister content of the electrolyte.

Abstract: A fast organic field effect transistor (100), which operates at low voltages, is achieved by the introduction of an oligomeric or polymeric electrolyte (131) between the gate electrode (141) and the organic semiconductor layer (121), which electrolyte (131) has a dissociation constant of at least 10?8. Said organic semiconductor layer (121) is in contact with the source electrode (111) and the drain electrode (112) of the transistor. In operation a potential (152) applied to said gate electrode (141) controls the current A between said source electrode (111) and said drain electrode (112).

Abstract: In a method in the fabrication of a ferroelectric memory device comprising a memory layer sandwiched between first and second electrode sets, the memory layer as well as both electrode sets are each realized in the memory device by a suitable printing process.

Abstract: In an organic electronic circuit, particularly a memory circuit with an organic ferroelectric or electret material the active material comprises fluorine atoms and consists of various organic materials. The active material is located between a first electrode and a second electrode. A cell with a capacitor-like structure is defined in the active material and can be accessed for an addressing operation via the first and the second electrode. At least one of these electrodes comprises a layer of chemically modified gold. In a passive matrix-addressable electronic device, particularly a ferroelectric or electret memory device, circuits of this kind with the active material as a ferroelectric or electret memory material form the elements of a matrix-addressable array and define the memory cells provided between first and second set of addressing electrodes. At least the electrodes of at least one of the sets then comprise at least a layer of gold.

Abstract: An organic electronic device consists of one or more electro-active organic or polymer materials sandwiched between electrodes. Critical in such devices is the interface between the electrode and the polymer, where degradation or chemical reaction products may develop that are deleterious to the proper functioning of the device. This is solved by introducing a functional interlayer composed of one or more materials consisting of a molecular backbone bearing phosphonate or phosphate functions, either directly attached or through side chains, said functional layer being disposed between at least one of the respective electrodes and said one or more electro-active materials in the device.

Abstract: In a method for enhancing the data storage capability of ferroelectric or electret memory cell which has been applied to storage of data and attained an imprint condition, suitable voltage pulses are used for evoking a temporary relaxation of the imprint condition into a volatile polarization state that can be discriminated from the imprinted polarization state in a non-destructive readout operation. Sequences of one or more voltage pulses are used to evoke readout signals respectively indicative of a non-volatile and a volatile polarization state of the memory cell, but without altering said polarization states.

Abstract: In a method for operating a passive matrix-addressable ferroelectric or electret memory device, a voltage pulse protocol based on a 1/3 voltage selection rule is used in order to keep disturb voltages at minimum, the voltage pulse protocol comprising cycles for read and write/erase bases on time sequence of voltage pulses with defined parameters. The method comprises a refresh procedure wherein cells for refresh are selected and refresh requests processed by a memory device controller, the refresh requests are monitored and processed in regard of ongoing or scheduled memory operations, and refresh voltage pulses with defined parameters are applied to the memory cells selected for refresh, while simultaneously ensuring that non-selected memory cells are subjected to zero voltage or voltages which do not affect the polarization state of these cells.

Abstract: In a memory and/or data processing device having at least two stacked layers which are supported by a substrate or forming a sandwiched self-supporting structure, wherein the layers include memory and/or processing circuitry with mutual connections between the layers and/or to circuitry in the substrate, the layers the are mutually arranged such that contiguous layers form a staggered structure on at least one edge of the device and at least one electrical edge conductor is provided passing over the edge on one layer and down one step at a time, enabling the connection to an electrical conductor in any of the following layers in the stack. A method for manufacturing a device of this kind includes the steps for adding the layers successively, one layer at a time, such that the layers form a staggered structure, and for providing one or more layers with at least one electrical contact pad for linking to one or more interlayer edge connectors.

Abstract: A method of driving a passive matrix display or memory array of cells comprising an electrically polarizable material exhibiting hysteresis, in particular a ferroelectric material, wherein the polarization state of individual cells can be switched by application of electric potentials or voltages to word and bit lines in the matrix or array.

Abstract: In a method in the fabrication of an organic thin-film semiconducting device comprising an electrode arrangement with electrodes contacting a semiconducting organic material, an anode in the electrode arrangement is made as a two-layer structure, where the first layer is a conducting or semiconducting material or a combination thereof deposited on a substrate and a second layer is a conducting polymer with a work function higher than that of the material in the first layer. A third layer consisting of semiconducting organic material and forming the active material of the device is deposited on the top of the anode, and the cathode made of a fourth layer of a metal deposited on a third layer. In a preferred embodiment a low work function metal is used in the first layer, a doped conjugated polymer such as PEDOT-PSS in the second layer, while the cathode may be formed of the same metal as used in the first layer.

Abstract: In a method of driving a passive matrix display or memory array of cells comprising an electrically polarizable material exhibiting hysteresis, in particular a ferroelectric material, wherein the polarization state of individual cells can be switched by application of electric potentials or voltages to word and bit lines in the matrix or array, a potential on selected word and bit lines is controlled to approach or coincide with one of n predefined potential levels and the potentials on all word and bit lines are controlled in time according to a protocol such that word lines are sequentially latched to potentials selected among nWORD potentials, while the bit lines are either latched sequentially to potentials selected among nBIT potentials, or during a certain period of a timing sequence given by the protocol connected to circuitry for detecting charges flowing between a bit line or bit lines and cells connecting thereto.

Abstract: A data storage/processing apparatus includes ROM and/or WORM and/or REWRITEABLE memory modules and/or processing modules provided as a single main layer or multiple main layers on top of a substrate. Transistors and/or diodes operate the apparatus. In one set of embodiments, at least some of the transistors and/or diodes are provided on or in the substrate. In another set of embodiments, at least some of the layers on the top of the substrate include low-temperature compatible organic materials and/or low temperature compatible processes inorganic films, and the transistors and/or diodes need not be disposed on or in the substrate. In a related fabricating method, the memory and/or processing modules are provided on the substrate by depositing the layers in successive steps under thermal conditions that avoid subjecting an already-deposited, processed underlying layers to static or dynamic temperatures exceeding given stability limits, particularly with regard to organic materials.

Abstract: In a scalable data processing apparatus, particularly a data storage apparatus, one or more thin-film devices which form a substantially planar layer comprise a plurality of sublayers of thin film. Two or more thin-film devices are provided as an integrated stack of the substantially planar layers which form the thin-film devices, such that the apparatus thereby forms a stacked configuration. Each thin-film device comprises one or more memory areas which form matrix addressable memories and additionally circuit areas which form electronic thin-film circuitry for controlling, driving and addressing memory cells in one or more memories. Each memory device has an interface to every other thin-film device in the apparatus, said interfaces being realized with communication and signal lines as well as supporting circuitry for processing extending vertically through dedicated interface areas in the thin-film device.