Patents by Inventor G. Sidney Cox

G. Sidney Cox has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9596757
    Abstract: The present disclosure is directed to a circuit board having a first imaged metal layer, a first electrically insulating layer, a second imaged metal layer, a polyimide bondply derived from 100 mole % 3,3?,4,4?-biphenyl tetracarboxylic dianhydride, 20 to 90 mole % 2,2?-bis(trifluoromethyl)benzidine, and 10 to 80 mole % 4,4?-oxydianiline, a third imaged metal layer, a second electrically insulating layer and a forth imaged metal layer. The circuit board does not have an adhesive layer between the second imaged metal layer and the polyimide bondply or the third imaged layer and the polyimide bondply.
    Type: Grant
    Filed: June 21, 2013
    Date of Patent: March 14, 2017
    Assignee: E I DU PONT DE NEMOURS AND COMPANY
    Inventors: G. Sidney Cox, Christopher Dennis Simone, Carl Robert Haeger
  • Publication number: 20150197073
    Abstract: The present disclosure is directed to a polyimide metal clad laminate. The metal clad laminate has a metal foil and a polyimide layer. The polyimide layer having a polyimide derived from 100 mole % 3,3?,4,4?-biphenyl tetracarboxylic dianhydride, and 100 mole % 2,2?-bis(trifluoromethyl)benzidine. The polyimide metal clad laminate does not have an adhesive layer between the metal foil and the polyimide layer.
    Type: Application
    Filed: June 21, 2013
    Publication date: July 16, 2015
    Inventors: G Sidney Cox, Christopher Dennis Simone, Carl Robert Haeger
  • Publication number: 20150201490
    Abstract: The present disclosure is directed to a circuit board having a first imaged metal layer, a first electrically insulating layer, a second imaged metal layer, a polyimide bondply derived from 100 mole % 3,3?,4,4?-biphenyl tetracarboxylic dianhydride, 20 to 90 mole % 2,2?-bis(trifluoromethyl)benzidine, and 10 to 80 mole % 4,4?-oxydianiline, a third imaged metal layer, a second electrically insulating layer and a forth imaged metal layer. The circuit board does not have an adhesive layer between the second imaged metal layer and the polyimide bondply or the third imaged layer and the polyimide bondply.
    Type: Application
    Filed: June 21, 2013
    Publication date: July 16, 2015
    Inventors: G. Sidney Cox, Christopher Dennis Simone, Carl Robert Haeger
  • Patent number: 7813141
    Abstract: This invention relates to a capacitive/resistive device, which may be embedded within a layer of a printed wiring board. Embedding the device conserves board surface real estate, and reduces the number of solder connections, thereby increasing reliability. More specifically, the device, comprises a first metallic foil; a second metallic foil; a first electrode formed from the first metallic foil; a dielectric disposed over the first electrode; a resistor element formed on and adjacent to the dielectric; a conductive trace; and a second electrode formed from the second metallic foil and disposed over the dielectric and in electrical contact with the resistor element, wherein the dielectric is disposed between the first electrode and the second electrode and wherein said dielectric comprises an unfilled polymer of dielectric constant less than 4.0.
    Type: Grant
    Filed: August 8, 2008
    Date of Patent: October 12, 2010
    Assignee: E. I. du Pont de Nemours and Company
    Inventors: William J. Borland, G. Sidney Cox, David Ross McGregor
  • Patent number: 7621041
    Abstract: The present invention relates to methods of forming multilayer structures and the structures themselves. In one embodiment, a method of forming a multilayer structure comprises: providing a dielectric composition comprising paraelectric filler and polymer wherein the paraelectric filler has a dielectric constant between 50 and 150; applying the dielectric composition to a carrier film thus forming a multilayer film comprising a dielectric layer and carrier film layer; laminating the multilayer film to a circuitized core wherein the dielectric layer of the multilayer film is facing the circuitized core; and removing the carrier film layer from the dielectric layer prior to processing; applying a metallic layer to the dielectric layer wherein the circuitized core, dielectric layer and metallic layer form a planar capacitor; and processing the planar capacitor to form a multilayer structure.
    Type: Grant
    Filed: June 13, 2006
    Date of Patent: November 24, 2009
    Assignee: E. I. du Pont de Nemours and Company
    Inventors: Sounak Banerji, G. Sidney Cox, Karl Hartmann Dietz
  • Publication number: 20090118408
    Abstract: The present disclosure relates to a dielectric composition having a resin and a filler. The filler is used to raise the dielectric and has a passivating surface coating thereon.
    Type: Application
    Filed: November 5, 2007
    Publication date: May 7, 2009
    Inventors: G. Sidney Cox, Thomas Edward Carney, Michele L. Ostraat, Stephen Mazur
  • Patent number: 7495887
    Abstract: A polymeric dielectric composition is disclosed, having a paraelectric filler with a dielectric constant between 50 and 150. Such compositions are well suited for electronic circuitry, such as, multilayer printed circuits, flexible circuits, semiconductor packaging and buried film capacitors.
    Type: Grant
    Filed: December 15, 2005
    Date of Patent: February 24, 2009
    Assignee: E.I. du Pont de Nemours and Company
    Inventor: G. Sidney Cox
  • Publication number: 20080297274
    Abstract: This invention relates to a capacitive/resistive device, which may be embedded within a layer of a printed wiring board. Embedding the device conserves board surface real estate, and reduces the number of solder connections, thereby increasing reliability. More specifically, the device, comprises a first metallic foil; a second metallic foil; a first electrode formed from the first metallic foil; a dielectric disposed over the first electrode; a resistor element formed on and adjacent to the dielectric; a conductive trace; and a second electrode formed from the second metallic foil and disposed over the dielectric and in electrical contact with the resistor element, wherein the dielectric is disposed between the first electrode and the second electrode and wherein said dielectric comprises an unfilled polymer of dielectric constant less than 4.0.
    Type: Application
    Filed: August 8, 2008
    Publication date: December 4, 2008
    Inventors: WILLIAM J. BORLAND, G. Sidney Cox, David Ross McGregor
  • Patent number: 7430128
    Abstract: This invention relates to a capacitive/resistive device, which may be embedded within a layer of a printed wiring board. Embedding the device conserves board surface real estate, and reduces the number of solder connections, thereby increasing reliability. More specifically, the device, comprises a first metallic foil; a second metallic foil; a first electrode formed from the first metallic foil; a dielectric disposed over the first electrode, a resistor element formed on and adjacent to the dielectric; a conductive trace; and a second electrode formed from the second metallic foil and disposed over the dielectric and in electrical contact with the resistor element, wherein the dielectric is disposed between the first electrode and the second electrode and wherein said dielectric comprises an unfilled polymer of dielectric constant less than 4.0. This invention also relates to a method of making the device.
    Type: Grant
    Filed: October 18, 2004
    Date of Patent: September 30, 2008
    Assignee: E.I. du Pont de Nemours and Company
    Inventors: William J. Borland, G. Sidney Cox, David Ross McGregor
  • Patent number: 7382627
    Abstract: A capacitive/resistive device provides both resistive and capacitive functions. The capacitive/resistive device may be embedded within a layer of a printed wiring board. Embedding the capacitive/resistive device conserves board surface real estate, and reduces the number of solder connections, thereby increasing reliability. Conserves board surface real estate, and reduces the number of solder connections, thereby increasing reliability.
    Type: Grant
    Filed: October 18, 2004
    Date of Patent: June 3, 2008
    Assignee: E.I. du Pont de Nemours and Company
    Inventors: William J. Borland, G. Sidney Cox, David Ross McGregor
  • Publication number: 20060082980
    Abstract: A capacitive/resistive device provides both resistive and capacitive functions. The capacitive/resistive device may be embedded within a layer of a printed wiring board. Embedding the capacitive/resistive device conserves board surface real estate, and reduces the number of solder connections, thereby increasing reliability.
    Type: Application
    Filed: October 18, 2004
    Publication date: April 20, 2006
    Inventors: William Borland, G. Sidney Cox, David Ross McGregor