Abstract: A semiconductor measurement apparatus may include an illumination unit configured to irradiate light to the sample, an image sensor configured to receive light reflected from the sample and output multiple interference images representing interference patterns of polarization components of light, an optical unit in a path through which the image sensor receives light and including an objective lens above the sample, and a control unit configured to obtain, by processing the multi-interference image, measurement parameters determined from the polarization components at each of a plurality of azimuth angles defined on a plane perpendicular to a path of light incident to the image sensor. The control unit may be configured to determine a selected critical dimension to be measured from a structure in the sample based on measurement parameters. The illumination unit and/or the optical unit may include a polarizer and a compensator having a ¼ wave plate.

Abstract: A semiconductor chip includes a write clock buffer, a voltage regulator, a process calibration circuit and a temperature calibration circuit. The voltage regulator generates plural regulated voltages. The process calibration circuit output one of the regulated voltages as a bias voltage of the write clock buffer, depending on a process variation of the semiconductor chip. The temperature calibration circuit track a temperature variation of the semiconductor chip in real time, performs analog calibration on the bias voltage from the process calibration circuit in real time depending on a result of the tracking, and outputs the analog-calibrated bias voltage to the write clock buffer.

Abstract: An electronic device may include a first housing, a second housing slidably coupled to the first housing along a first direction, and a flexible display disposed to be supported by the first housing and the second housing. The electronic device may include a support member disposed under the flexible display to support at least a portion of the flexible display. The support member may include an elastic body including a first surface facing the flexible display and a second surface facing the opposite direction to the first surface, and a plurality of shafts at least partially embedded in the elastic body and spaced apart from each other at predetermined intervals, and each of the plurality of shafts may be disposed to have a length in a second direction perpendicular to the first direction.

Abstract: A display apparatus including: a display panel including an emission line and a pixel electrically connected to the emission line; an emission driver configured to output an emission signal to the emission line; and a driving controller configured to determine a light emission cycle, wherein the light emission cycle is a number of light emissions in a single frame of the emission signal, wherein the driving controller is configured to determine a luminance according to a user luminance setting and a grayscale value of input image data, to determine the light emission cycle corresponding to a range of the luminance and to determine an off ratio according to the luminance, wherein the off ratio is a ratio of turned-off gate lines to a total number of the gate lines.

Abstract: A memory device includes a memory cell array including a plurality of memory cells; a voltage generator configured to generate voltages used for a program operation and a verify operation for the memory cells; and control logic configured to perform a plurality of program loops while writing data to the memory cell array, such that first to N-th (e.g., N>=1) program loops including a program operation and a verify operation are performed and at least two program loops in which the verify operation is skipped are performed when a pass/fail determination of the program operation in the N-th program loop indicates a pass.

Abstract: A memory device includes a memory cell array including M memory cells connected to one bit line and configured to distributively store N-bit data, where N is a natural number of 2 or more and M is a natural number of 2 or more and less than or equal to N, the M memory cells including a first memory cell and a second memory cell having different sensing margins, and a memory controller including a page buffer, the memory controller configured to distributively store the N-bit data in the M memory cells and to sequentially read data stored in the M memory cells to obtain the N-bit data, and an operation logic configured to execute an operation using the N-bit data, the memory controller configured to provide different reading voltages to the first memory cell and the second memory cell.

Abstract: A memory device includes a memory cell array including a plurality of memory cells; a voltage generator configured to generate voltages used for a program operation and a verify operation for the memory cells; and control logic configured to perform a plurality of program loops while writing data to the memory cell array, such that first to N-th (e.g., N>=1) program loops including a program operation and a verify operation are performed and at least two program loops in which the verify operation is skipped are performed when a pass/fail determination of the program operation in the N-th program loop indicates a pass.

Abstract: A memory device includes a memory cell array including M memory cells connected to one bit line and configured to distributively store N-bit data, where N is a natural number and M is a natural number of 2 or more and N or less, the M memory cells including a first memory cell and a second memory cell having different sensing margins, and a memory controller including a page buffer, the memory controller configured to distributively store the N-bit data in the M memory cells and to sequentially read data stored in the M memory cells to obtain the N-bit data, and an operation logic configured to execute an operation using the N-bit data, the memory controller configured to provide different reading voltages to the first memory cell and the second memory cell.

Abstract: Disclosed is a semiconductor device used to embody a neuromorphic computation system and operation method thereof. By comprising a floating body as a short-term memory means electrically isolated from the surroundings and a long-term memory means formed at one side of the floating body not formed of a source, a drain and a gate, a low power synaptic semiconductor device is provided, which can be mimic not only the short-term memory in a nervous system of a living body by an impact ionization, but also the short- and long-term memory transition property and the causal inference property of a living body due to the time difference of signals of the pre- and post-synaptic neurons.

Abstract: Disclosed is a semiconductor device used to embody a neuromorphic computation system and operation method thereof. By comprising a floating body as a short-term memory means electrically isolated from the surroundings and a long-term memory means formed at one side of the floating body not formed of a source, a drain and a gate, a low power synaptic semiconductor device is provided, which can be mimic not only the short-term memory in a nervous system of a living body by an impact ionization, but also the short- and long-term memory transition property and the causal inference property of a living body due to the time difference of signals of the pre- and post-synaptic neurons.