Patents by Inventor Ga Won Lee

Ga Won Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6943125
    Abstract: Provided is a method for manufacturing a semiconductor device including a plurality of different semiconductor elements with a transistor for fabricating the semiconductor device formed on a semiconductor substrate, an interlayer insulation film formed all over the upper part, and a hole trap site formed in the interlayer insulation film for preventing a mobile ion like H or moisture from penetrating, whereby it can be prevented that a leakage current increases abnormally where the voltage difference (Vgs) is lower than a threshold voltage.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: September 13, 2005
    Assignee: Hynix Semiconductor Inc.
    Inventors: Ga Won Lee, Jae Hoon Choi, Jae Chul Om, Sung Wook Park, Jae Hee Lee
  • Publication number: 20040219799
    Abstract: Provided is a method for manufacturing a semiconductor device including a plurality of different semiconductor elements with a transistor for fabricating the semiconductor device formed on a semiconductor substrate, an interlayer insulation film formed all over the upper part, and a hole trap site formed in the interlayer insulation film for preventing a mobile ion like H or moisture from penetrating, whereby it can be prevented that a leakage current increases abnormally where the voltage difference (Vgs) is lower than a threshold voltage.
    Type: Application
    Filed: December 18, 2003
    Publication date: November 4, 2004
    Inventors: Ga Won Lee, Jae Hoon Choi, Jae Chul Om, Sung Wook Park, Jae Hee Lee
  • Publication number: 20040185658
    Abstract: The present invention relates to a method of forming an interlayer dielectric film in a semiconductor device. More particularly, the present invention selectively forms an insulating film spacer only at a region where a plug is formed between metal lines and removes the insulating film spacer at a region where the plug is not formed to lower the aspect ratio between the metal lines, in a process of burying an insulating material between the metal lines to electrically insulate them. Therefore, the present invention can easily bury the insulating material even between the metal lines having a narrow gap without voids.
    Type: Application
    Filed: March 29, 2004
    Publication date: September 23, 2004
    Applicant: Hynix Semiconductor Inc.
    Inventor: Ga Won Lee
  • Patent number: 6790685
    Abstract: A method of forming a test pattern includes: forming first and second junction regions having a symmetrical structure on both side of field oxide layer formed on a semiconductor substrate; forming third and fourth junction regions having a asymmetrical structure on front and rear portions of the field oxide layer; forming a test pattern having first and second projection portions on the semiconductor substrate, in which both side portions of the test pattern are overlapped with the first and second junction regions and the first and second projection portions which are formed on front and rear portions of the test pattern are overlapped with the third and fourth junction regions; forming an inter insulating layer on a resulting structure after forming the test pattern; patterning the inter insulating layer to expose a portion of the first to fourth junction regions; forming current supply lines connected to the first and second junction regions, respectively; and forming voltage measuring lines connected to t
    Type: Grant
    Filed: May 2, 2002
    Date of Patent: September 14, 2004
    Assignee: Hynix Semiconductor Inc.
    Inventor: Ga Won Lee
  • Patent number: 6723589
    Abstract: The present invention relates to a method of manufacturing a thin film transistor in a semiconductor device. The present invention forms a single crystal silicon thin film on an interlayer insulating film on a single crystal driver transistor using a solid phase crystallization of amorphous silicon, forms a single crystal silicon thin film transistor (C—Si TFT) in the single crystal silicon thin film in order to uses it as a load transistor and uses a contact plug connecting a drain in the driver transistor and a drain in the load transistor as a SPC (solid phase crystallization) plug, in a process of depositing a silicon thin film on a single crystal transistor by a three-dimensional stack process to deposit to form a load transistor in a manufacture process of SRAM. Therefore, the present invention can improve the uniformity and reliability of the load transistor.
    Type: Grant
    Filed: December 27, 2001
    Date of Patent: April 20, 2004
    Assignee: Hynix Semiconductor Inc.
    Inventor: Ga Won Lee
  • Publication number: 20030209758
    Abstract: The present invention discloses a transistor of a semiconductor device and a method for forming the same which provides improved electrical characteristics of the transistor and allow a high integration density of the device wherein a super steep halo doped region is formed according to a halo implant process using a gate and a dummy gate as masks by reducing a halo dose in source/drain junction regions in order to prevent deterioration of characteristic of the device.
    Type: Application
    Filed: December 27, 2002
    Publication date: November 13, 2003
    Inventors: Ga Won Lee, Jae Hee Lee
  • Publication number: 20030119272
    Abstract: The present invention discloses a capacitor of a semiconductor device and a method for forming the same which has sufficient capacitance for high integration of the semiconductor device. A stack structure of a first capacitor and a second capacitor is formed to be connected to a semiconductor substrate. Here, the first and second capacitors are vertically spaced apart and electrically insulated from each other, and the adjacent capacitors are formed on different layers. Accordingly, sufficient capacitance for high integration of the semiconductor device is obtained to improve reliability of the semiconductor device and achieve high integration thereof.
    Type: Application
    Filed: December 26, 2002
    Publication date: June 26, 2003
    Inventor: Ga Won Lee
  • Publication number: 20030100132
    Abstract: A method of forming a test pattern includes: forming first and second junction regions having a symmetrical structure on both side of field oxide layer formed on a semiconductor substrate; forming third and fourth junction regions having a asymmetrical structure on front and rear portions of the field oxide layer; forming a test pattern having first and second projection portions on the semiconductor substrate, in which both side portions of the test pattern are overlapped with the first and second junction regions and the first and second projection portions which are formed on front and rear portions of the test pattern are overlapped with the third and fourth junction regions; forming an inter insulating layer on a resulting structure after forming the test pattern; patterning the inter insulating layer to expose a portion of the first to fourth junction regions; forming current supply lines connected to the first and second junction regions, respectively; and forming voltage measuring lines connected to t
    Type: Application
    Filed: May 2, 2002
    Publication date: May 29, 2003
    Applicant: Hynix Semiconductor Inc.
    Inventor: Ga Won Lee
  • Publication number: 20030022484
    Abstract: The present invention relates to a method of forming an interlayer dielectric film in a semiconductor device. More particularly, the present invention selectively forms an insulating film spacer only at a region where a plug is formed between metal lines and removes the insulating film spacer at a region where the plug is not formed to lower the aspect ratio between the metal lines, in a process of burying an insulating material between the metal lines to electrically insulate them. Therefore, the present invention can easily bury the insulating material even between the metal lines having a narrow gap without voids.
    Type: Application
    Filed: December 28, 2001
    Publication date: January 30, 2003
    Applicant: Hynix Semiconductor Inc.
    Inventor: Ga Won Lee
  • Publication number: 20020197794
    Abstract: The present invention relates to a method of manufacturing a thin film transistor in a semiconductor device. The present invention forms a single crystal silicon thin film on an interlayer insulating film on a single crystal driver transistor using a solid phase crystallization of amorphous silicon, forms a single crystal silicon thin film transistor (C—Si TFT) in the single crystal silicon thin film in order to uses it as a load transistor and uses a contact plug connecting a drain in the driver transistor and a drain in the load transistor as a SPC (solid phase crystallization) plug, in a process of depositing a silicon thin film on a single crystal transistor by a three-dimensional stack process to deposit to form a load transistor in a manufacture process of SRAM. Therefore, the present invention can improve the uniformity and reliability of the load transistor.
    Type: Application
    Filed: December 27, 2001
    Publication date: December 26, 2002
    Applicant: Hynix Semiconductor Inc.
    Inventor: Ga Won Lee