Abstract: A service provider or operator of a network often requires the ability to control the amount of data that flows can send and/or receive over a network such that a flow receives at least a predetermined, minimum amount of upstream and/or downstream bandwidth and can potentially utilize excess upstream and/or downstream bandwidth above the minimum amount when available. The present disclosure provides a method and apparatus for implementing a control scheme capable of achieving these and other objectives in a network. In general, the method and apparatus probabilistically meter packets to be sent upstream and/or downstream to determine whether they are in conformance with a service agreement (and at what level of conformance). By using probabilistic metering, smaller width counters can be used to perform the metering over conventional implementations, which reduces power demands and chip space demands.

Abstract: A service provider or operator of a network often requires the ability to control the amount of data that flows can send and/or receive over a network such that a flow receives at least a predetermined, minimum amount of upstream and/or downstream bandwidth and can potentially utilize excess upstream and/or downstream bandwidth above the minimum amount when available. The present disclosure provides a method and apparatus for implementing a control scheme capable of achieving these and other objectives in a network. In general, the method and apparatus probabilistically meter packets to be sent upstream and/or downstream to determine whether they are in conformance with a service agreement (and at what level of conformance). By using probabilistic metering, smaller width counters can be used to perform the metering over conventional implementations, which reduces power demands and chip space demands.

Abstract: A method (10) for compressing a data structure representing a layout of a multi layered VLSI device, the method comprising of the steps of; (11) Receiving the data structure; said data structure comprising a plurality of layer portions, each layer portion represents a single layer out of the plurality of layers; each layer comprises of functional elements and non functional elements, where the non functional elements are inserted between functional elements to provide a planar layout. (12) Generating a non-functional elements locating data structure representing the non functional elements of all layers. (13) Deleting representations of non functional elements from the data structure and adding the compressed non functional elements data structure to generate a compressed data structure representing the layout of the multi layered VLSI device.