Abstract: Described herein is a mismatch shaping technique applied in digital-to-analog converters (DACs) for high pass filtering mismatch related errors. The mismatch shaping scheme is based on a zero mean error encoding technique, which can be applied directly to binary coded signals, without the use for binary to thermometer decoding and element shuffling. In at least one example, an apparatus is provided which comprises a mismatch shaping circuitry to receive an N-bit binary input bits and to generate an (N+1)-bit digital output. In at least one example, the apparatus further comprises a digital-to-analog converter to receive the (N+1)-bit digital output and to generate an analog output, wherein the mismatch shaping circuitry is to encode the (N+1)-bit digital output to shape mismatch errors in the digital-to-analog converter.

Abstract: A comparator-based buffer method and system enhance the driving capability of high-gain amplifiers with switched-capacitor loads. It includes a current source, a comparator, switches, sampling capacitor and overshoot correction resistor. A correction solution using a resistor in the charging path and a correction phase reduces the overshoot of the output voltage while constraining power consumption and minimizing components. Spectre® simulations verify the effectiveness of the invention.

Abstract: A method and apparatus for an adder-embedded dynamic preamplifier system with dynamic comparator and current mode adder including differential switches for precharging, a switch for evaluation; and reference, feedfoward input sections. When differential switches are closed, OUTN and OUTP are precharged. During the evaluation, discharging currents are proportionately determined by input and reference values. A following latch amplifies the discharging differences of OUTN and OUTP.

Abstract: A method and apparatus for a modified noise-coupled modulator using zero optimization technique is disclosed. By realizing the resonator coefficient as a part of branches other than those of the main transfer function, the problem of improving SQNR without degrading other specifications is solved. Second order noise coupling is used to implement zeros without using feedback branches going into the first integrator. Embodiments use a first-order modulator, second-order noise coupling and a resonator. It allows lower power consumption and smaller size by removing small capacitor values and gain factors and reducing the number of amplifiers.

Abstract: A method and apparatus are provided for Fast Data Weighted Average (DWA) double-sampling modulators with minimal loop delay supporting improved stability. Quantization and DEM are accomplished within non-overlap time. By this reduction in time delay, power can be saved for analog integrators. The DC signal of partitioned DWA is removed by alternating reference voltages, and there is no additional delay as the alternation is performed at the comparator inputs. Embodiments employ an oversampling ratio (OSR) of 8 and a 15-level quantizer.

Abstract: An apparatus and method for a fast quantizer comparator comprising three stages: a preamplifier stage, a regeneration latch stage, and a data latch stage. Time delay is reduced by changing the initial voltages of the regeneration latch outputs. The current source is provided at the tail of the comparator, enabling time delay optimization. When the PMOS equalization switch turns off, it makes the clock signal feedthrough and provides charge injection into the outputs. Because of these charges, the time delay of the comparator is variable. Only a very low current sets the output voltages because the resetting time is longer than the comparison time.

Abstract: A method and apparatus are provided for Fast Data Weighted Average (DWA) double-sampling modulators with minimal loop delay supporting improved stability. Quantization and DEM are accomplished within non-overlap time. By this reduction in time delay, power can be saved for analog integrators. The DC signal of partitioned DWA is removed by alternating reference voltages, and there is no additional delay as the alternation is performed at the comparator inputs. Embodiments employ an oversampling ratio (OSR) of 8 and a 15-level quantizer.

Abstract: A method and apparatus for an adder-embedded dynamic preamplifier system with dynamic comparator and current mode adder including differential switches for precharging, a switch for evaluation; and reference, feedfoward input sections. When differential switches are closed, OUTN and OUTP are precharged. During the evaluation, discharging currents are proportionately determined by input and reference values. A following latch amplifies the discharging differences of OUTN and OUTP.

Abstract: A comparator-based buffer method and system enhance the driving capability of high-gain amplifiers with switched-capacitor loads. It includes a current source, a comparator, switches, sampling capacitor and overshoot correction resistor. A correction solution using a resistor in the charging path and a correction phase reduces the overshoot of the output voltage while constraining power consumption and minimizing components. Spectre® simulations verify the effectiveness of the invention.

Abstract: A method and apparatus for a modified noise-coupled modulator using zero optimization technique is disclosed. By realizing the resonator coefficient as a part of branches other than those of the main transfer function, the problem of improving SQNR without degrading other specifications is solved. Second order noise coupling is used to implement zeros without using feedback branches going into the first integrator. Embodiments use a first-order modulator, second-order noise coupling and a resonator. It allows lower power consumption and smaller size by removing small capacitor values and gain factors and reducing the number of amplifiers.

Abstract: A hybrid delta sigma ADC architecture and method is disclosed to implement a high-resolution delta-sigma modulator with a single-bit output. The system contains a low-order multi-bit analog noise-shaping loop, followed by a high-order single-bit digital modulator. The combination simplifies the analog modulator, and allows the use of most of the full-scale input range.

Abstract: A hybrid delta sigma ADC architecture and method is disclosed to implement a high-resolution delta-sigma modulator with a single-bit output. The system contains a low-order multi-bit analog noise-shaping loop, followed by a high-order single-bit digital modulator. The combination simplifies the analog modulator, and allows the use of most of the full-scale input range.

Abstract: A signal scaling circuit for accurately reducing the effective amplitude of an input signal by a rational factor N/M, where N and M are integers and N<M, is disclosed. An input, reference, bias and output node as well as control circuitry are selectively coupled to M switched capacitor circuits such that N/M scaling may be achieved. Cooperation between the M switched capacitor circuits and the control circuitry divides the M switched capacitors circuits into subsets of N and M?N switched capacitors, respectively. Each subset is then selectively coupled to an input, reference and/or bias signal to produce an output signal having as one of its components an N/M portion of the input signal. Error reduction in the scaled signal is achieved by shuffling the switched capacitor circuits populating each subset after selected time intervals.

Abstract: Systems and methods receive a digital signal and generate an analog signal indicative thereof. In one embodiment, a system includes a DAC that receives a multi-bit digital signal, generates at least two analog signals each indicative of the value of the multi-bit digital signal, and filters two or more of the at least two analog signals. In another embodiment, a system includes a DAC that receives digital input signals at an input data rate and outputs analog signals Indicative of the digital signals to a signal conditioning stage at an output data rate different the input data mute.

Abstract: An oversampling D/A converter system achieves high linearity and low quantization error by using dual internal D/A converters: one with high linearity but high quantization error and the other with low linearity but low quantization error. A signal path in the system includes an L-bit quantizer for quantizing a digital input signal into an L-bit signal plus a quantization error and a D/A converter for converting the L-bit signal and quantization error into an analog signal. A correction path that parallels the signal path includes an M-bit quantizer, where M is greater than L, and an M-bit D/A converter. A signal generated by the correction path cancels the shaped quantization error of the signal generated by the signal path by adding the negative of the shaped quantization error to the signal of the signal path. The resulting analog signal is filtered by a low-pass analog filter to extract the analog equivalent of the digital input signal.

Abstract: A precision sigma-delta analog-to-digital converter disposed to operate at a sampling rate giving rise to a relatively low oversampling ratio is disclosed herein. The high-order sigma-delta analog-to-digital converter (10) of the present invention is operative to convert an analog input signal to a digital output sequence. The inventive converter (10) includes a first integrating network (14) for generating a first sampled analog signal (X.sub.1) in response to the analog input signal. A second integrating network (18) generates a second sampled analog signal (X.sub.2) in response to the first sampled analog signal (X.sub.1). A third integrating network (22) generates a third sampled analog signal (X.sub.3) in response to the second sampled analog signal (X.sub.2). The sigma-delta converter (10) of the present invention further includes an internal quantizer (24) for generating the digital output sequence in response to the third sampled analog signal.

Abstract: A precision sigma-delta A/D converter having a desired number of cascaded stages is disclosed herein. The multi-stage sigma-delta analog-to-digital converter (10) of the present invention is operative to convert an analog input signal X(z) to an output sequence of digital words. The converter (10) of the present invention includes a first sigma-delta converter stage (14) for generating a first sequence of digital words and a quantization error signal in response to the analog input signal X(z). An interstage amplifier (34) then amplifies the quantization error signal by a first gain factor G. The present invention further includes a second sigma-delta converter stage (18) for generating a second sequence of digital words in response to the amplified quantization error signal. The first and second sequences are next filtered by a digital noise cancellation network (31, 32) and the filtered second sequence is divided by the first gain factor G via a divider circuit (38).

Abstract: A pipelined digital to analog converter is disclosed which utilizes a series of three capacitor and switch sections to convert a three bit segment of a digital word into an analog voltage. For a ten bit digital word, three 3-capacitor sections would be required with an additional capacitor section. The voltage across the output, or last, capacitor is the analog voltage in direct relation to the input digital word. Each of the three capacitor sections works in relation to switched transistors to charge and discharge in a predetermined fashion said capacitors, in relation to the binary level of each of the three digits in the input digital word. The circuit operates from the least significant bit to the most significant bit, and converts the input digital word to an output analog voltage.

Abstract: A switched capacitor pseudo-N-path filter stage includes an analog integrator circuit having an input, an output, and a feedback capacitor connected between the input and the output. A plurality of storage capacitors are connected across the feedback capacitor and an input capacitor is provided. The feedback capacitor and storage capacitors form an analog random access memory. A switching circuit selectively connects the input capacitor across electrical ground and between an input signal and the input of the integrator circuit, and also selectively connects the feedback capacitor and the storage capacitors between electrical ground and the output of the integrator circuit. In this manner, the input signal is filtered as the input capacitor samples the input signal and the charge on the input capacitor is circulated through the feedback capacitor and the storage capacitors.

Abstract: A solid state imager wherein a pixel non-uniformity correction system compensates for photosite non-uniformities by providing a linear correction method and utilizing three modes: mode #1--dark current detection, mode #2--uniform illumination, and mode #3--data detection mode. In the first calibration cycle, the outputs of all the photocells on an imager 10, representing "dark current" are stored in an "offset" memory 14. In the second calibration cycle, a uniform illumination from a constant light level is applied to the imager 10. This uniform illumination signal is passed to an arithmetic unit 18 where the dark current signal is subtracted from it and the difference is then stored in gain memory 28. The gain memory passes this signal back to the arithmetic unit 18, so that in the third mode, the data detection mode, the arithmetic unit 18 can electronically correct the data signals that were non-uniformly affected by the internal characteristics of the imager.