Abstract: A transistor device includes transistor cells each having source and drift regions of a first doping type and a body region of a second doping type in a first region of a semiconductor body, and a gate electrode dielectrically insulated from the body region. A gate conductor arranged on top of a second region of the semiconductor body is electrically connected to each gate electrode. A source conductor arranged on top of the first region is connected to each source and body region. A discharging region of the second doping type is arranged in the second region and located at least partially below the gate conductor, and includes at least one lower dose section in which a doping dose is lower than a minimum doping dose in other sections of the discharging region. The at least one lower dose section is associated with a corner of the gate conductor.

Abstract: In an embodiment, a method of fabricating a superjunction semiconductor device includes implanting first ions into a first region of a first epitaxial layer using a first implanting apparatus and nominal implant conditions to produce a first region in the first epitaxial layer comprising the first ions and a first implant characteristic and implanting second ions into a second region of the first epitaxial layer, the second region being laterally spaced apart from the first region, using second nominal implanting conditions estimated to produce a second region in the first epitaxial layer having the second ions and a second implant characteristic that lies within an acceptable maximum difference of the first implant characteristic.

Abstract: A semiconductor device includes: a semiconductor substrate having a bulk oxygen concentration of at least 6×1017 cm?3; an epitaxial layer on a first side of the semiconductor substrate, the epitaxial layer and the semiconductor substrate having a common interface; a superjunction semiconductor device structure in the epitaxial layer; and an interface region extending from the common interface into the semiconductor substrate to a depth of at least 10 ?m. A mean oxygen concentration of the interface region is lower than the bulk oxygen concentration of the semiconductor substrate.

Abstract: A semiconductor wafer includes an alignment mark contained within in a kerf region of the semiconductor wafer. The alignment mark includes a groove vertically extending from a main surface of the semiconductor wafer to a bottom surface of the groove, and at least one tin protruding from the bottom surface of the groove. The groove has a rectangular shape with four sidewalls and four inside corners, with each of the four inside corners facing the at least one fin. A minimum distance between the at least one fin and a nearest one of the four inside corners is at least 25 ?m.

Abstract: A transistor device comprises at least one gate electrode, a gate runner connected to the at least one gate electrode and arranged on top of a semiconductor body, a plurality of gate pads arranged on top of the semiconductor body, and a plurality of resistor arrangements. Each gate pad is electrically connected to the gate runner via a respective one of the plurality of resistor arrangements, and each of the resistor arrangements has an electrical resistance, wherein the resistances of the plurality of resistor arrangements are different.

Abstract: A transistor device includes transistor cells each having source and drift regions of a first doping type and a body region of a second doping type in a first region of a semiconductor body, and a gate electrode dielectrically insulated from the body region. A gate conductor arranged on top of a second region of the semiconductor body is electrically connected to each gate electrode. A source conductor arranged on top of the first region is connected to each source and body region. A discharging region of the second doping type is arranged in the second region and located at least partially below the gate conductor, and includes at least one lower dose section in which a doping dose is lower than a minimum doping dose in other sections of the discharging region. The at least one lower dose section is associated with a corner of the gate conductor.

Abstract: A semiconductor device includes: a semiconductor substrate having a bulk oxygen concentration of at least 6×1017 cm?3; an epitaxial layer on a first side of the semiconductor substrate, the epitaxial layer and the semiconductor substrate having a common interface; a superjunction semiconductor device structure in the epitaxial layer; and an interface region extending from the common interface into the semiconductor substrate to a depth of at least 10 ?m. A mean oxygen concentration of the interface region is lower than the bulk oxygen concentration of the semiconductor substrate.

Abstract: A semiconductor wafer includes an alignment mark contained within in a kerf region of the semiconductor wafer. The alignment mark includes a groove vertically extending from a main surface of the semiconductor wafer to a bottom surface of the groove, and at least one tin protruding from the bottom surface of the groove. The groove has a rectangular shape with four sidewalls and four inside corners, with each of the four inside corners facing the at least one fin. A minimum distance between the at least one fin and a nearest one of the four inside corners is at least 25 ?m.

Abstract: A method for forming semiconductor device includes providing a semiconductor substrate having an initial surface oxygen concentration in a surface region of less than 6×1017 cm?3, forming an epitaxial layer on a first side of the semiconductor substrate, and implanting dopants into the epitaxial layer. An optional thermal anneal is carried out prior to forming the epitaxial layer and/or a thermal treatment is carried out after implanting dopants.

Abstract: An alignment mark in a process surface of a semiconductor layer includes a groove with a minimum width of at least 100 ?m and a vertical extension in a range 100 nm to 1 ?m. The alignment mark further includes at least one fin within the groove at a distance of at least 60 ?m to a closest one of inner corners of the groove.

Abstract: A transistor device comprises at least one gate electrode, a gate runner connected to the at least one gate electrode and arranged on top of a semiconductor body, a plurality of gate pads arranged on top of the semiconductor body, and a plurality of resistor arrangements. Each gate pad is electrically connected to the gate runner via a respective one of the plurality of resistor arrangements, and each of the resistor arrangements has an electrical resistance, wherein the resistances of the plurality of resistor arrangements are different.

Abstract: A semiconductor device includes an electrically conductive lead frame which includes a die pad and a plurality of electrically conductive leads, each of the leads in the plurality being spaced apart from the die pad. The semiconductor device further includes first and second integrated switching devices mounted on the die pad, each of the first and second integrated switching devices include electrically conductive gate, source and drain terminals. The source terminal of the first integrated switching device is disposed on a rear surface of the first integrated switching device that faces and electrically connects with the die pad. The drain terminal of the second integrated switching device is disposed on a rear surface of the second integrated switching device that faces and electrically connects with the die pad.

Abstract: A semiconductor device includes a semiconductor body having first and second opposite sides, a drift region, a body layer at the second side, and a field-stop region in Ohmic connection with the body layer. A source metallization at the second side is in Ohmic connection with the body layer. A drain metallization at the first side is in Ohmic connection with the drift region. A gate electrode at the second side is electrically insulated from the semiconductor body to define an operable switchable channel region in the body layer. A through contact structure extends at least between the first and second sides, and includes a conductive region in Ohmic connection with the gate electrode and a dielectric layer. In a normal projection onto a horizontal plane substantially parallel to the first side, the field-stop region surrounds at least one of the drift region and the gate electrode.

Abstract: An alignment mark in a process surface of a semiconductor layer includes a groove with a minimum width of at least 100 ?m and a vertical extension in a range 100 nm to 1 ?m. The alignment mark further includes at least one fin within the groove at a distance of at least 60 ?m to a closest one of inner corners of the groove.

Abstract: An alignment mark in a process surface of a semiconductor layer includes a groove with a minimum width of at least 100 ?m and a vertical extension in a range 100 nm to 1 ?m. The alignment mark further includes at least one fin within the groove at a distance of at least 60 ?m to a closest one of inner corners of the groove.

Abstract: According to an embodiment of a method of forming a semiconductor device, a semiconductor layer including a first dopant species of a first conductivity type and a second dopant species of a second conductivity type different from the first conductivity type is formed. The semiconductor layer is part of a semiconductor body having opposite first and second surfaces. Trenches are formed in the semiconductor layer at the first surface. The trenches are filled with a filling material including at least a semiconductor material. A thermal oxide is formed at one or both of the first and second surfaces, the thermal oxide having a thickness of at least 200 nm. Thermal processing of the semiconductor body causes diffusion of the first and second dopants species into the filling material.

Abstract: A semiconductor device includes an electrically conductive lead frame which includes a die pad and a plurality of electrically conductive leads, each of the leads in the plurality being spaced apart from the die pad. The semiconductor device further includes first and second integrated switching devices mounted on the die pad, each of the first and second integrated switching devices include electrically conductive gate, source and drain terminals. The source terminal of the first integrated switching device is disposed on a rear surface of the first integrated switching device that faces and electrically connects with the die pad. The drain terminal of the second integrated switching device is disposed on a rear surface of the second integrated switching device that faces and electrically connects with the die pad.

Abstract: A method for forming semiconductor device includes providing a semiconductor substrate having an initial surface oxygen concentration in a surface region of less than 6×1017 cm?3, forming an epitaxial layer on a first side of the semiconductor substrate, and implanting dopants into the epitaxial layer. An optional thermal anneal is carried out prior to forming the epitaxial layer and/or a thermal treatment is carried out after implanting dopants.

Abstract: In an embodiment, a method of fabricating a superjunction semiconductor device includes implanting first ions into a first region of a first epitaxial layer using a first implanting apparatus and nominal implant conditions to produce a first region in the first epitaxial layer comprising the first ions and a first implant characteristic and implanting second ions into a second region of the first epitaxial layer, the second region being laterally spaced apart from the first region, using second nominal implanting conditions estimated to produce a second region in the first epitaxial layer having the second ions and a second implant characteristic that lies within an acceptable maximum difference of the first implant characteristic.

Abstract: A semiconductor device includes a semiconductor body having first and second opposite sides, a drift region, a body layer at the second side, and a field-stop region in Ohmic connection with the body layer. A source metallization at the second side is in Ohmic connection with the body layer. A drain metallization at the first side is in Ohmic connection with the drift region. A gate electrode at the second side is electrically insulated from the semiconductor body to define an operable switchable channel region in the body layer. A through contact structure extends at least between the first and second sides, and includes a conductive region in Ohmic connection with the gate electrode and a dielectric layer. In a normal projection onto a horizontal plane substantially parallel to the first side, the field-stop region surrounds at least one of the drift region and the gate electrode.