Patents by Inventor Gabor Temes

Gabor Temes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11595009
    Abstract: A slewing mitigation technique is presented where just the right amount of charge is provided at the switching instant to a switch capacitor circuit so that operational transconductance amplifier (OTA) does not need to provide high peak current. This eliminates slewing altogether and allows using OTAs with less static current for the same settling accuracy.
    Type: Grant
    Filed: July 29, 2021
    Date of Patent: February 28, 2023
    Assignee: Oregon State University
    Inventors: Manjunath Kareppagoudr, Gabor Temes, Jyotindra Shakya, Emanuel Caceres
  • Publication number: 20220038064
    Abstract: A slewing mitigation technique is presented where just the right amount of charge is provided at the switching instant to a switch capacitor circuit so that operational transconductance amplifier (OTA) does not need to provide high peak current. This eliminates slewing altogether and allows using OTAs with less static current for the same settling accuracy.
    Type: Application
    Filed: July 29, 2021
    Publication date: February 3, 2022
    Applicant: Oregon State University
    Inventors: Manjunath Kareppagoudr, Gabor Temes, Jyotindra Shakya, Emanuel Caceres
  • Publication number: 20050212591
    Abstract: A signal scaling circuit for accurately reducing the effective amplitude of an input signal by a rational factor N/M, where N and M are integers and N<M, is disclosed. An input, reference, bias and output node as well as control circuitry are selectively coupled to M switched capacitor circuits such that N/M scaling may be achieved. Cooperation between the M switched capacitor circuits and the control circuitry divides the M switched capacitors circuits into subsets of N and M-N switched capacitors, respectively. Each subset is then selectively coupled to an input, reference and/or bias signal to produce an output signal having as one of its components an N/M portion of the input signal. Error reduction in the scaled signal is achieved by shuffling the switched capacitor circuits populating each subset after selected time intervals.
    Type: Application
    Filed: March 23, 2004
    Publication date: September 29, 2005
    Inventors: Gabor Temes, Janos Markus, Jose Silva