Abstract: Devices and methods for charging a power storage device using a piezoelectric energy-harvest charger that employs a single switched inductor stage. The charger may maintain a maximum power point without requiring a second switched inductor stage.

Abstract: A circuit for harvesting electrical energy from a piezoelectric source and for storing the electrical energy in a battery includes an inductor that is configured to store electrical energy. A diode bridge-free switching network is configured to: direct electrical energy from the piezoelectric source to the inductor during a first portion of a piezoelectric charge generating cycle; and direct electrical energy from the inductor to the battery during a second portion of the piezoelectric charge generating cycle.

Abstract: A circuit for harvesting electrical energy from a piezoelectric source and for storing the electrical energy in a battery includes an inductor that is configured to store electrical energy. A diode bridge-free switching network is configured to: direct electrical energy from the piezoelectric source to the inductor during a first portion of a piezoelectric charge generating cycle; and direct electrical energy from the inductor to the battery during a second portion of the piezoelectric charge generating cycle.

Abstract: A circuit arrangement with a gate driver circuit for a power transistor is disclosed which is suitable for low voltage applications, permitting a rail-to-rail output without a loss in speed/bandwidth, which is very simple, low cost, low current and area efficient. The gate driver circuit comprises a drain follower with a MOS driver transistor having the gate connected to an interconnection node of a capacitive divider. A first capacitor of the capacitive divider is connected between the drain and the gate and a second capacitor is connected between the gate and an input of the gate driver circuit. The gate driver has the required low impedance for driving the gate of the power transistor.

Abstract: A circuit arrangement with a gate driver circuit for a power transistor is disclosed which is suitable for low voltage applications, permitting a rail-to-rail output without a loss in speed/bandwidth, which is very simple, low cost, low current and area efficient. The gate driver circuit comprises a drain follower with a MOS driver transistor having the gate connected to an interconnection node of a capacitive divider. A first capacitor of the capacitive divider is connected between the drain and the gate and a second capacitor is connected between the gate and an input of the gate driver circuit. The gate driver has the required low impedance for driving the gate of the power transistor.

Abstract: A low dropout voltage regulator (100; 300) comprises a supply input terminal (102; 302) for connecting a supply voltage (VDD) and an output terminal (104; 304) for providing a regulated output voltage (V0), a reference voltage source (130; 330); and an output voltage monitor (120; 320). An error amplifier (132; 332) has an output (138; 338) supplying an error signal (Verr) in response to deviations of the regulated output voltage (Vout) from a desired target output voltage value (V0) at the output terminal (104; 304). A power output FET (110; 310), has a drain-source channel connected between the supply input terminal (102; 302) and the output terminal (104; 304) of the voltage regulator, and a gate terminal (116; 316). The gate terminal of the power output FET (110; 310) is controlled by the error amplifier (132; 332) via a driver FET (140; 340) in such a way that any deviations of the regulated output voltage (Vout) from a desired target output voltage value (V0) are minimized.

Abstract: A high power supply ripple rejection internally compensated low drop-out voltage regulator using an output PMOS pass device. The voltage regulator uses an intermediate amplifier stage configured from a common source, current mirror loaded PMOS device to replace the more conventional source follower impedance buffer associated with conventional Miller compensation techniques. Compensation is achieved through use of a small internal capacitor that provides a very low frequency dominant pole at the output of the input stage while effectively pushing out the two other poles at the outputs of the second and third gain stages to a frequency well outside of the unity gain frequency to ensure closed loop stability. High, wide bandwidth PSRR is achieved through an integrated circuit implementation of three voltage gain stages compensated by a nested active Miller compensation technique that does not impedance shunt the output series PMOS pass device.

Abstract: A low drop-out (LDO) voltage regulator (10) and system (100) including the same are disclosed. An error amplifier (38) controls the gate voltage of a source follower transistor (24) in response to the difference between a feedback voltage (VFB) from the output (VOUT) and a reference voltage (VREF). The source of the source follower transistor (24) is connected to the gates of an output transistor (12), which drives the output (VOUT) from the input voltage (VIN) in response to the source follower transistor (24). A current mirror transistor (14) has its gate also connected to the gate of the output transistor (12), and mirrors the output current at a much reduced ratio. The mirror current is conducted through network of transistors (18, 22), and controls the conduction of a first feedback transistor (28) and a second feedback transistor (35) which are each connected to the source of the source follower transistor (24) and in parallel with a weak current source (34).

Abstract: A compensated amplifier, for amplifying an input signal applied to an input node to provide an output signal at an amplifier output node. The compensated amplifier includes a first amplifier stage having an internal node as an input thereto and having a first stage output node. Also included is a second amplifier stage coupled to the first amplifier stage, having the input node as an input thereto and providing the output signal at the amplifier output node. A capacitor is coupled between the output node and the internal node.