Abstract: A sensor assembly includes a controller, a sensor, and a housing. The housing encloses the controller and sensor and includes a body supporting the controller and a head supporting the sensor. The body prevents exposure of the controller to an external environment, and the head includes slots enabling exposure of the sensor to the external environment.

Abstract: A Wireless Regional Area Network (WRAN) receiver comprises a transceiver for communicating with a wireless network over one of a number of channels, and an Advanced Television Systems Committee (ATSC) signal detector for use in forming a supported channel list comprising those ones of the number of channels upon which an ATSC signal was not detected, wherein the ATSC signal detector is a threshold-based detector and detects an ATSC signal as a function of at least one threshold, and wherein the ATSC signal detector is responsive to at least one of a carrier tracking loop lock signal, a symbol timing recovery lock signal and a synchronization (sync) lock signal.

Abstract: A Wireless Regional Area Network (WRAN) receiver comprises a transceiver for communicating with a wireless network over one of a number of channels, and an Advanced Television Systems Committee (ATSC) signal detector for use in forming a supported channel list comprising those ones of the number of channels upon which an ATSC signal was not detected, wherein the ATSC signal detector is a threshold-based detector and detects an ATSC signal as a function of at least one threshold, and wherein the ATSC signal detector is responsive to at least one of a carrier tracking loop lock signal, a symbol timing recovery lock signal and a synchronization (sync) lock signal.

Abstract: There are provided, in a clock generator for generating a plurality of output clock signals, an apparatus and method for synchronizing the clock generator to an input reference clock in the presence of a jittery input clock provided to the clock generator from a PLL. The clock generator and the PLL each have a divider with the same ratio. The apparatus includes a synchronizer (205) and a state machine (210). The synchronizer receives the input reference clock and the jittery input clock, and generates there from a synchronized input clock signal with respect to the jittery input clock. The state machine receives the synchronized input clock signal and the jittery input clock, synchronizes with the synchronized input clock signal using the jittery input clock, and abstains from a re-synchronizing operation when the jittery input clock has a jitter of up to a pre-defined maximum number of clock widths.

Abstract: A centroid calculator calculates the channel virtual center for an adaptive equalizer, based on some type of training signal (e.g., the segment sync of a ATSC-DTV signal), with internal limiting capability that improves its performance. In addition, a centroid calculator with internal limiting capability that improves performance.

Abstract: A receiver comprises a demodulator for providing a demodulated signal and a centroid calculator responsive to the demodulated signal for identifying a correct carrier phase for use in the centroid calculation and in removing carrier phase ambiguity in the demodulator. In addition, the centroid calculator may include a limiter.

Abstract: A television set includes an ATSC (Advanced Television Systems Committee) receiver, which includes an NTSC (National Television Systems Committee) co-channel interference detector based on carrier tracking of the NTSC video carrier signal. The NTSC co-channel interference detector includes a carrier tracking loop and a decision device. The carrier tracking loop processes a received signal for detecting the possible presence of the NTSC video carrier signal and for providing a tracking signal representative thereof. The decision device receives the tracking signal and recovers a DC offset therefrom. The decision device then determines that NTSC co-channel interference is present if the DC offset signal is greater than a predefined threshold.

Abstract: There are provided, in a clock generator for generating a plurality of output clock signals, an apparatus and method for synchronizing the clock generator to an input reference clock in the presence of a jittery input clock provided to the clock generator from a PLL. The clock generator and the PLL each have a divider with the same ratio. The apparatus includes a synchronizer (205) and a state machine (210). The synchronizer receives the input reference clock and the jittery input clock, and generates there from a synchronized input clock signal with respect to the jittery input clock. The state machine receives the synchronized input clock signal and the jittery input clock, synchronizes with the synchronized input clock signal using the jittery input clock, and abstains from a re-synchronizing operation when the jittery input clock has a jitter of up to a pre-defined maximum number of clock widths.

Abstract: A receiver comprises a demodulator for providing a demodulated signal and a centroid calculator responsive to the demodulated signal for identifying a correct carrier phase for use in the centroid calculation and in removing carrier phase ambiguity in the demodulator. In addition, the centroid calculator may include a limiter.

Abstract: An ATSC (Advanced Television Systems Committee) VSB (Vestigial Sideband) receiver includes a carrier tracking loop (CTL) for processing a received ATSC VSB signal and a CTL lock detector. The CTL lock detector includes an averaging filter for averaging the down-converted received ATSC VSB signal to provide a DC offset, an estimator for providing an estimate of the DC offset, and a comparator for providing a lock signal as a function of a comparison between the estimate of the DC offset and the DC offset, wherein the lock signal is representative of either a locked condition or an unlocked condition of the CTL.

Abstract: A receiver comprises a sync generator for providing a synchronization signal, wherein the sync generator comprises at least two modes of operation, wherein in a first mode of operation the sync generator generates the synchronization signal as a function of a channel virtual center signal and in a second mode of operation the dual-mode sync generator generates the synchronization signal as a function of a correlation signal.

Abstract: A centroid calculator calculates the channel virtual center for an adaptive equalizer, based on some type of training signal (e.g., the segment sync of a ATSC-DTV signal), with internal limiting capability that improves its performance. In addition, a centroid calculator with internal limiting capability that improves performance.

Abstract: A demodulator for a high definition television receiver includes a first circuit element which receives a signal, and is operative in a first arrangement to produce an output signal having a first dynamic range, and operative in a second arrangement to produce an output signal having a second dynamic range different from the first dynamic range. A second circuit element is arranged for optimally processing a signal having a substantially predetermined fixed dynamic range. A gain control circuit is coupled between the first and second circuit elements, and produces a signal having the substantially predetermined fixed dynamic range.

Abstract: A television set includes an ATSC (Advanced Television Systems Committee) receiver, which includes an NTSC (National Television Systems Committee) co-channel interference detector based on carrier tracking of the NTSC video carrier signal. The NTSC co-channel interference detector includes a carrier tracking loop and a decision device. The carrier tracking loop processes a received signal for detecting the possible presence of the NTSC video carrier signal and for providing a tracking signal representative thereof. The decision device receives the tracking signal and recovers a DC offset therefrom. The decision device then determines that NTSC co-channel interference is present if the DC offset signal is greater than a predefined threshold.

Abstract: A communications receiver receives a signal which has not been filtered by a matched pulse shaping filter. In the receiver, a circuit element processes the received signal and as a part of that process introduces additional linear distortion into the processed received signal. A matched filter, coupled to the circuit element, generates a fully matched filtered signal compensated for the distortion intrinsic to the received signal pulse shape and the distortion introduced by the circuit element.

Abstract: A symbol timing recovery detector receives a sample stream, representing an input signal having successive symbol times sampled at successive sample times. The sample stream includes samples representing successive symbols alternating with samples representing transitions between surrounding symbol representative samples. The detector includes a first circuit which determines a transition value from a transition representative sample and surrounding symbol representative samples. A second circuit determines the slope between the surrounding symbol representative samples. A third circuit generates a signal representing the phase error between the sample times and the symbol times of the input signal from the slope and the transition value.

Abstract: A demodulator for a high definition television receiver includes a first circuit element which receives a signal, and is operative in a first arrangement to produce an output signal having a first dynamic range, and operative in a second arrangement to produce an output signal having a second dynamic range different from the first dynamic range. A second circuit element is arranged for optimally processing a signal having a substantially predetermined fixed dynamic range. A gain control circuit is coupled between the first and second circuit elements, and produces a signal having the substantially predetermined fixed dynamic range.

Abstract: A communications receiver receives a signal which has not been filtered by a matched pulse shaping filter. In the receiver, a circuit element processes the received signal and as a part of that process introduces additional linear distortion into the processed received signal. A matched filter, coupled to the circuit element, generates a fully matched filtered signal compensated for the distortion intrinsic to the received signal pulse shape and the distortion introduced by the circuit element.

Abstract: A symbol timing recovery detector receives a sample stream, representing an input signal having successive symbol times sampled at successive sample times. The sample stream includes samples representing successive symbols alternating with samples representing transitions between surrounding symbol representative samples. The detector includes a first circuit which determines a transition value from a transition representative sample and surrounding symbol representative samples. A second circuit determines the slope between the surrounding symbol representative samples. A third circuit generates a signal representing the phase error between the sample times and the symbol times of the input signal from the slope and the transition value.

Abstract: A multi-protocol serial data bus system includes two clock lines and a data line. A controller generates a first clock signal and a first data signal according to a first serial data bus protocol during a first mode of operation of the system, and generates a second clock signal and a second data signal according to a second serial data bus protocol during a second mode of operation. The first clock signal and the first data signal are provided on the first and third signal paths, respectively, during the first mode of operation. The second clock signal and the second data signal are provided on the second and third signal paths, respectively, during the second mode of operation.