Abstract: A method and apparatus for estimating signal related delays in a PLD design is disclosed. The PLD design is modeled in relation to one or more stages, each of the stages including a driver and one or more receivers coupled to the driver with a wiring tree. The modeling is based on a selected set of parameters that include: slope related delays associated with the driver; a delay related to a layout of the wiring tree; and a parameter related to a slope transfer from a previous driver input. A predetermined set of values for each of the selected parameters are accessed; the estimated signal related delays are computed for each of the modeled stages; and are written to a computer-readable storage medium.