Abstract: Computational requirements are reduced for executing simulation code for a logic circuit design having at least some elements which are synchronously clocked by multiple phase clock signals, the logic design being subject to resistive conflicts and to charge sharing, the simulation code including data structures associated with circuit modules and nodes interconnecting the circuit modules. A three-state version of simulation code is generated for the circuit design, the three states corresponding to states 0, 1, or X, where X represents an undefined state. A preanalysis was performed of the three-state version and phase waveforms are stored each representing values occurring at a node of the code. For each phase of a module for which no event-based evaluation need be performed, an appropriate response to an event occurring with respect to the module of the three-state version is determined and stored.

Abstract: Computational requirements are reduced for executing simulation code for a logic circuit design having at least some elements which are synchronously clocked by multiple phase clock signals, the simulation code including data structures associated with circuit modules and nodes interconnecting the circuit modules. The simulation code is preanalyzed and phase waveforms are stored each representing values occurring at a node in successive phases. Based on the preanalysis, modules are categorized in a first category, for which an event-based evaluation is to be performed in each phase of the simulation, and a second category for which no event-based evaluation need be performed in at least one but not all phases. For each phase of a second category module, an appropriate response to an event occurring with respect to the module is determined.