Abstract: An external environment recognition device 101 estimates a blind spot region around a host vehicle based on information detected by a sensor that detects a target around the host vehicle. The external environment recognition device 101 includes a visibility index determination unit 121 that calculates a visibility index of the target based on a coordinate point and a reflection intensity of the target detected by the sensor, and assigns the visibility index to a region from the host vehicle 200 to the coordinate point of the target, a visibility map storage unit 124 that stores the visibility index as a visibility map in association with the region, and a blind spot region estimation unit 127 that estimates the blind spot region based on the visibility map.

Abstract: An external environment recognition device 101 estimates a blind spot region around a host vehicle based on information detected by a sensor that detects a target around the host vehicle. The external environment recognition device 101 includes a visibility index determination unit 121 that calculates a visibility index of the target based on a coordinate point and a reflection intensity of the target detected by the sensor, and assigns the visibility index to a region from the host vehicle 200 to the coordinate point of the target, a visibility map storage unit 124 that stores the visibility index as a visibility map in association with the region, and a blind spot region estimation unit 127 that estimates the blind spot region based on the visibility map.

Abstract: A semiconductor device is provided which is formed of a wafer having on a surface thereof an area efficient arrangement of at least two antifuses in vertically stacked relation and sharing a common intermediate electrode therebetween. The arrangement includes at least one lower antifuse having a lower counter electrode and a lower fusible insulator portion defining a lower fuse element of an initial high electrical resistance state which interconnects the lower counter electrode with the common intermediate electrode, and at least one upper antifuse, which may be the same as or different from the lower antifuse, the upper antifuse having an upper counter electrode and an upper fusible insulator portion defining an upper fuse element of an initial high electrical resistance state which interconnects the upper counter electrode with the common intermediate electrode.

Abstract: A semiconductor device is provided which is formed of a wafer having on a surface thereof an area efficient arrangement of at least two antifuses in vertically stacked relation and sharing a common intermediate electrode therebetween. The arrangement includes at least one lower antifuse having a lower counter electrode and a lower fusible insulator portion defining a lower fuse element of an initial high electrical resistance state which interconnects the lower counter electrode with the common intermediate electrode, and at least one upper antifuse, which may be the same as or different from the lower antifuse, the upper antifuse having an upper counter electrode and an upper fusible insulator portion defining an upper fuse element of an initial high electrical resistance state which interconnects the upper counter electrode with the common intermediate electrode.

Abstract: A circuit for programming electrical fuses, in accordance with the present invention, includes a shift register including a plurality of latches. Each latch has a corresponding switch and a corresponding electrical fuse. A bit generator generates a single bit of a first state and all other bits of a second state. The bit generator propagates the generated bits into the shift register in accordance with a clock signal. Each switch enables conduction through the corresponding electrical fuse in accordance with the generated bits stored in the corresponding latch. A blow voltage line connects to the electrical fuses. The blow voltage line is activated to blow fuses in accordance with programming data such that the electrical fuses are programmed in accordance with the programming data when the single bit of the first state is stored in the latch corresponding to the fuse to be programmed.

Abstract: A fuse latch for a memory circuit according to the present invention comprises a plurality of address lines, a control signal line provided from a fuse, a multiplexer for multiplexing the plurality of address lines in response to the control signal wherein the multiplexer has only one type transistors, and a decoder for receiving a multiplexed signal from the multiplexer. Since the multiplexer has a smaller size than that of a conventional CMOS multiplexer, a fuse latch circuit of the present invention has a smaller size than that of a conventional fuse latch. The multiplexer preferably has only NMOS transistors. To overcome a voltage drop due to an NMOS threshold voltage, the present invention uses low-threshold NMOSs and/or boosts the transistors in the multiplexer. Alternatively, the voltage drop is successfully converted into a CMOS level by using a dynamic logic circuit.

Abstract: A fuse latch for a memory circuit according to the present invention comprises a plurality of address lines, a control signal line provided from a fuse, a multiplexer for multiplexing the plurality of address lines in response to the control signal wherein the multiplexer has only one type transistors, and a decoder for receiving a multiplexed signal from the multiplexer. Since the multiplexer has a smaller size than that of a conventional CMOS multiplexer, a fuse latch circuit of the present invention has a smaller size than that of a conventional fuse latch. The multiplexer preferably has only NMOS transistors. To overcome a voltage drop due to an NMOS threshold voltage, the present invention uses low-threshold NMOSs and/or boosts the transistors in the multiplexer. Alternatively, the voltage drop is successfully converted into a CMOS level by using a dynamic logic circuit.

Abstract: A plurality of fuses of different types, each type of fuse serving a specific purpose are positioned on a semiconductor integrated circuit wafer, wherein activating one type of fuse does not incapacitate fuses of a different type. Fuses of the first type, e.g., laser activated fuses, are primarily used for repairing defects at the wafer level, whereas fuses of the second type, e.g., electrically activated fuses, are used for repairing defects found after mounting the IC chips on a module and stressing the module at burn-in test. Defects at the module level typically are single cell failures which are cured by the electrically programmed fuses to activate module level redundancies.

Abstract: A circuit for storing a bit of data is provided, where the circuit includes a first fuse having a first end and a second end and a second fuse having a third end and a fourth end. The first end of the first fuse is connected to a logic 0 input and its second end is connected to a common output. The third end of the second fuse is connected to a logic 1 input and the fourth end is connected to the common output. To store the bit of data, one of the first and second fuses is selectively blown. Hence, two fuses can be used to store a bit of information.

Abstract: A memory device that includes a plurality of data storage cells; at least one redundancy data storage cell; a redundancy match detection circuit; and a means for coupling programmable fuses to the redundancy match detection circuit, wherein a defective data storage is replaced by one redundancy data storage when the redundancy match detection detects a pre-determined condition set by said programmable fuse is described. Decoding is accomplished by a data bus selecting the e-fuse to be blown. The data bus is also used for reading the state of the e-fuses to ensure that the e-fuses are correctly blown. Power is effectively applied to the selected e-fuses while sharing the data bus for e-fuse decoding and verification. In order to reduce the number of communication channels between e-fuses and the redundancy match detection circuitry, the transfer operation uses time multiplexing, allowing e-fuse information to be transferred to the redundancy match detection circuitry sequentially.

Abstract: The present disclosure relates to semiconductor memories and more particularly, to an improved method and apparatus for replacing defective row/column lines. In accordance with the present invention, a high replacement flexibility redundancy and method is employed to increase chip yield and prevent sense amplifier signal contention. Redundancy elements are integrated in at least two of a plurality of memory arrays, which don't share the sense amplifiers. Thus, no additional sense amplifiers are required. A defective row/column line in a first array or block is replaced with a redundant row/column line from its own redundancy. A corresponding row/column line whether defective or not is replaced in a second array or block, which does not share sense amplifiers with the first block. The corresponding row/column is replaced to mimic the redundancy replacement of the first block thereby increasing flexibility and yield as well as preventing sensing signal contention.

Abstract: A semiconductor device includes an array of electrical fuses having a structure which permits tight fuse pitches while enabling electrical fusing at voltages of about 10 volts or less. The fuses are useful to replace defective components of the device and/or to permit custom wiring. The semiconductor device includes a substrate with a tight pitch array of fuses including a plurality of fuse links of selective cross sectional area in closely adjacent arrangement, each connected at one end to an individual connector terminal of larger cross sectional area than that of the fuse link, and at another end to a common connector terminal of larger cross sectional area than that of the individual connector terminals. The common connector terminal is typically held at a less positive potential than one of the individual connector terminals during the time a fuse link thereat is to be opened such that electron flow is in a direction from the common connector terminal to the fuse link.

Abstract: Feedback pulse generators each have an input and an output, a first digital gating circuit, and a second digital gating circuit. The first digital gating circuit is coupled between the input and the output of the pulse generator, and is responsive to an input signal from an external source changing from a first logic state to a second logic state that is received at a first input thereof for initiating a pulse at the output of the pulse generator.