Patents by Inventor Gabriel E. Tanase

Gabriel E. Tanase has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12160212
    Abstract: A sensor offset voltage compensation circuit includes a programmable gain amplifier (PGA) having an input loop configured to receive the signal output by a sensor (e.g., a voltage generated a sensor resistive bridge of a pressure sensor) and an output loop configured to furnish an output signal having a voltage that is greater than the input voltage. An offset compensation voltage is applied to at least one of the input loop or the output loop of the PGA to at least substantially cancel the zero-quantity offset voltage of the sensor from the output voltage.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: December 3, 2024
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Gabriel E. Tanase, Walter Chi
  • Publication number: 20220231647
    Abstract: A sensor offset voltage compensation circuit includes a programmable gain amplifier (PGA) having an input loop configured to receive the signal output by a sensor (e.g., a voltage generated a sensor resistive bridge of a pressure sensor) and an output loop configured to furnish an output signal having a voltage that is greater than the input voltage. An offset compensation voltage is applied to at least one of the input loop or the output loop of the PGA to at least substantially cancel the zero-quantity offset voltage of the sensor from the output voltage.
    Type: Application
    Filed: December 23, 2021
    Publication date: July 21, 2022
    Inventors: Gabriel E. Tanase, Walter Chi
  • Patent number: 9985633
    Abstract: A voltage clamping system includes: (a) a first electronic device connected to a first power source and having a signal output node, a voltage clamp high node, and a voltage clamp low node, wherein the voltage clamp high node and the voltage clamp low node are coupled to a second power source different than the first power source; and (b) a second electronic device powered by the second power source and having a signal input node coupled to the signal output node of the first electronic device. The signal output node of the first electronic device is passively clamped, with low distortion, approximately rail-to-rail with respect to the second power source such that the second electronic device is protected from damage due to excessive voltage levels.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: May 29, 2018
    Assignee: MAXIM INTEGRATED PRODUCTS, INC.
    Inventors: Gabriel E. Tanase, Michael B. Francon
  • Patent number: 9804629
    Abstract: A method and apparatus for current sensing and measurement employs two cascaded MOSFET current mirrors, wherein the mirrored current leaving the first current mirror is fed to the input of the second current mirror. Each current mirror contains a high current MOSFET and a low current MOSFET, connected source-to-source and gate-to-gate. The MOSFETs are matched so that drain-to-source current flowing in the high current MOSFET is proportional to the drain-to-source current flowing in the low current MOSFET. The ratio of high current to low current for each current mirror is M, where M is 100 or less. Voltage biasing networks are employed to maintain constant drain-to-source voltages for both MOSFETs in each current mirror.
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: October 31, 2017
    Assignee: Maxim Integrated Products, Inc.
    Inventor: Gabriel E. Tanase
  • Patent number: 9608626
    Abstract: An integrated circuit with precision current source includes a first MOSFET, a second MOSFET, an op-amp and a resistor formed on a common semiconductor substrate. The first MOSFET is characterized by a first multiplier (×M1) and the second MOSFET is characterized by a second multiplier (×M2) where a ratio of ×M2 to ×M1 is greater than one. An inverting input of the op-amp is coupled to a drain of the first MOSFET and an output of the op-amp is coupled to a gate of the first MOSFET. A negative feedback circuit limits a rise in output current under low output voltage conditions.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: March 28, 2017
    Assignee: Maxim Integrated Products, Inc.
    Inventor: Gabriel E. Tanase
  • Patent number: 9444434
    Abstract: A voltage clamping system includes: (a) a first electronic device connected to a first power source and having a signal output node, a voltage clamp high node, and a voltage clamp low node, wherein the voltage clamp high node and the voltage clamp low node are coupled to a second power source different than the first power source; and (b) a second electronic device powered by the second power source and having a signal input node coupled to the signal output node of the first electronic device. The signal output node of the first electronic device is passively clamped, with low distortion, approximately rail-to-rail with respect to the second power source such that the second electronic device is protected from damage due to excessive voltage levels.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: September 13, 2016
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Gabriel E. Tanase, Michael B. Francon
  • Patent number: 9195252
    Abstract: A method and apparatus for current sensing and measurement employs two cascaded MOSFET current mirrors, wherein the mirrored current leaving the first current mirror is fed to the input of the second current mirror. Each current mirror contains a high current MOSFET and a low current MOSFET, connected source-to-source and gate-to-gate. The MOSFETs are matched so that drain-to-source current flowing in the high current MOSFET is proportional to the drain-to-source current flowing in the low current MOSFET. The ratio of high current to low current for each current mirror is M, where M is 100 or less. Voltage biasing networks are employed to maintain constant drain-to-source voltages for both MOSFETs in each current mirror.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: November 24, 2015
    Assignee: Maxim Integrated Products, Inc.
    Inventor: Gabriel E. Tanase
  • Patent number: 9163981
    Abstract: A gesture sensing device includes one or more sensors and a processor for processing sensed voltages output from the sensors based on ambient light and/or reflected light received by the sensors. The processor determines an ambient light level and/or a distance between the target and the sensors such that, if the ambient light level exceeds an ambient light threshold and/or the distance is less than a distance threshold, the processor determines the motion of a target relative to the sensors based on the ambient light instead of the reflected light.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: October 20, 2015
    Assignee: Maxim Integrated Products, Inc.
    Inventor: Gabriel E. Tanase
  • Patent number: 9148140
    Abstract: An integrated circuit with precision current source includes a first MOSFET, a second MOSFET, an op-amp and a resistor formed on a common semiconductor substrate. The first MOSFET is characterized by a first multiplier (xM1) and the second MOSFET is characterized by a second multiplier (xM2) where a ratio of xM2 to xM1 is greater than one. An inverting input of the op-amp is coupled to a drain of the first MOSFET and an output of the op-amp is coupled to a gate of the first MOSFET. A negative feedback circuit limits a rise in output current under low output voltage conditions.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: September 29, 2015
    Assignee: Maxim Integrated Systems, Inc.
    Inventor: Gabriel E. Tanase
  • Patent number: 9093992
    Abstract: A circuit is provided for both boosting output current and providing short circuit protection in an integrated circuit such as an operational amplifier. In an embodiment, a current-boosting output stage with short-circuit protection includes six current sources and six transistors, where the the boosting of output current is achieved using positive feedback and the short circuit protection is achieved using negative feedback.
    Type: Grant
    Filed: July 10, 2014
    Date of Patent: July 28, 2015
    Assignee: Maxim Integrated Products, Inc.
    Inventor: Gabriel E. Tanase
  • Patent number: 9030790
    Abstract: An electrostatic discharge (ESD) protection circuit, set forth by way of example and not limitation, includes an input operative to receive input signals and a primary protection circuit coupled to the input. The protection circuit is operative to provide a single ESD current path for one or more the input signals that are ESD strikes. The currents of positive ESD strikes and negative ESD strikes flow through the single ESD current path, where the single ESD current path is not used by one or more of the input signals that are non-ESD signals.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: May 12, 2015
    Assignee: Maxim Integrated Products Inc.
    Inventor: Gabriel E. Tanase
  • Publication number: 20140319326
    Abstract: A gesture sensing device includes one or more sensors and a processor for processing sensed voltages output from the sensors based on ambient light and/or reflected light received by the sensors. The processor determines an ambient light level and/or a distance between the target and the sensors such that, if the ambient light level exceeds an ambient light threshold and/or the distance is less than a distance threshold, the processor determines the motion of a target relative to the sensors based on the ambient light instead of the reflected light.
    Type: Application
    Filed: June 27, 2014
    Publication date: October 30, 2014
    Inventor: Gabriel E. Tanase
  • Patent number: 8742800
    Abstract: An integrated circuit with precision current source includes a first MOSFET, a second MOSFET, an op-amp and a resistor formed on a common semiconductor substrate. The first MOSFET is characterized by a first multiplier (xM1) and the second MOSFET is characterized by a second multiplier (xM2) where a ratio of xM2 to xM1 is greater than one. An inverting input of the op-amp is coupled to a drain of the first MOSFET and an output of the op-amp is coupled to a gate of the first MOSFET.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: June 3, 2014
    Assignee: Maxim Integrated Products, Inc.
    Inventor: Gabriel E. Tanase
  • Publication number: 20040021506
    Abstract: The present invention provides a method and apparatus to significantly improve the settling times of noise reduction filters in voltage reference circuits. Resistor-capacitor (RC) filter networks used as noise reduction filters in the present invention are provided switches, controlled through a logic pulse signal, which places the filter network into an alternate operation mode. This alternate operation mode periodically closes parallel switches allowing the filter network to pre-charge RC filter capacitors to a steady-state value at power-up, or during any other transient condition, at greater speeds by bypassing selected resistors within the RC filter network.
    Type: Application
    Filed: July 30, 2002
    Publication date: February 5, 2004
    Inventor: Gabriel E. Tanase
  • Patent number: 6538496
    Abstract: Low voltage, high impedance current mirrors realizable in MOS or junction transistor circuits and particularly suited for use in integrated circuits. The current mirrors use first and second transistors coupled as a differential pair with a tail current that may be part of the input current to be mirrored. Another component of the input current to be mirrored is applied to the drain/collector of the first transistor of the differential pair, with the gate/base of that transistor being coupled to a bias voltage. The voltage on the drain/collector of the first transistor is effectively inverted and used to control the gate/base of the second transistor to provide a drain/collector current in the second transistor equal to the difference between the tail current and the current in the drain/collector of the first transistor. Various embodiments are disclosed.
    Type: Grant
    Filed: September 28, 2000
    Date of Patent: March 25, 2003
    Assignee: Maxim Integrated Products, Inc.
    Inventor: Gabriel E. Tanase
  • Patent number: 6472858
    Abstract: Low voltage, fast settling precision current mirrors and methods. The precision current mirror have first and second current mirrors, each having an input to be mirrored and a mirror output, the current mirrors being coupled so that the mirror output of each current mirror receives part of the input to be mirrored by the other current mirror, the first current mirror also mirroring current for re-mirroring to the input of the second current mirror, and to a precision current mirror output in proportion to the current provided to the input of the second current mirror. Various embodiments are disclosed, including MOS and junction transistor embodiments, and an embodiment having increased output impedance. Details of the method are disclosed.
    Type: Grant
    Filed: September 28, 2000
    Date of Patent: October 29, 2002
    Assignee: Maxim Integrated Products, Inc.
    Inventor: Gabriel E. Tanase
  • Patent number: 6169445
    Abstract: A current mode transmitter is provided including a charge circuit connected to an enable node and adapted to generate a charge current upon the receipt of an activation signal at the enable node. Also included is a discharge circuit connected to the enable node and adapted to generate a discharge current upon the cessation of the receipt of the activation signal at the enable node. An output circuit is connected between an output node and the charge and discharge circuits. The output circuit serves for generating an output current at the output node in response to the charge current and the discharge current. Such output current is initiated within a first delay after the detection of the activation signal by the charge circuit. Further, the output current is terminated within a second delay after the detection of the cessation of the receipt of the activation signal by the discharge charge circuit.
    Type: Grant
    Filed: May 17, 1999
    Date of Patent: January 2, 2001
    Assignee: Maxim Integrated Products, Inc.
    Inventor: Gabriel E. Tanase
  • Patent number: 5990723
    Abstract: The present invention teaches a variety of filter circuits for protecting against transient electrical pulses such as those caused by electrostatic discharge (ESD) events. One aspect of the present invention teaches an integrated circuit package having primary circuitry, an ESD protection device, a filter circuit, and a conductive lead arranged to couple a point external to the integrated circuit package to a point internal to the integrated circuit package. The ESD device, coupled in series between the conductive lead and a ground reference, can limit the voltage magnitude of a transient electrical pulse occurring upon the conductive lead. The filter circuit is operable such that the voltage magnitude of an electrical signal generated at the filter circuit output is less than the voltage magnitude of the certain transient electrical pulse itself. One preferred filter circuit has two resistors R.sub.1 and R.sub.2, two capacitors C.sub.1 and C.sub.2, and two transistors Q.sub.1 and Q.sub.2.
    Type: Grant
    Filed: January 9, 1998
    Date of Patent: November 23, 1999
    Assignee: Maxim Integrated Products, Inc.
    Inventor: Gabriel E. Tanase
  • Patent number: 5414352
    Abstract: A parametric test circuit adapted for testing a device in two alternate modes of operation. In one mode, the circuit forces a voltage on the device under test and measures the current drawn. In the alternate mode, the circuit forces voltage on the device under test and measures the voltage. The same circuit components including a difference amplifier are used in both modes of operation, and they are merely reconfigured by a plurality of switches. Further, a plurality of range resistor sections are used, and the nonselected sections are prevented from interfering with the selected section by zero-biasing anti-parallel diode pairs in series with the nonselected range resistors.
    Type: Grant
    Filed: January 26, 1993
    Date of Patent: May 9, 1995
    Assignee: Raytheon Company
    Inventor: Gabriel E. Tanase