Patents by Inventor Gabriel George Barna

Gabriel George Barna has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8058161
    Abstract: A method of manufacturing a semiconductor device having shallow trench isolation includes steps of forming a hard mask layer on the substrate surface, etching a trench through the hard mask, filling the trench with an isolation material, forming a recessed trench, and forming a serpentine gate structure to connect electronic sources and drains.
    Type: Grant
    Filed: September 29, 2006
    Date of Patent: November 15, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Gabriel George Barna, Andrew Marshall, Brian K. Kirkpatrick
  • Publication number: 20100062587
    Abstract: A method of manufacturing a single-electron transistor device is provided. The method includes forming a thinned region in a silicon substrate, the thinned region offset by a non-selected region. The method also includes forming at least one quantum island from the thinned region by subjecting the thinned region to an annealing process. The non-selected region is aligned with the quantum island and tunnel junctions are formed between the quantum island and the non-selected region. The present invention also includes a single-electron device, and a method of manufacturing an integrated circuit that includes a single-electron device.
    Type: Application
    Filed: November 16, 2009
    Publication date: March 11, 2010
    Applicant: Texas Instruments Incorporated
    Inventors: Christoph Wasshuber, Gabriel George Barna, Olivier Alain Faynot
  • Patent number: 7642144
    Abstract: A method of manufacturing a semiconductor device having recessed active trenches by providing a substrate with STI and active regions, forming a first oxide layer on the substrate, forming an nitride layer on the first oxide layer, employing a photolithographic process to create at least one recessed active trench through the first oxide layer and the nitride layer and into the substrate to create an isolation region, wherein the at least one trench is perpendicular to at least one gate structure in an active area of the substrate, layering the trench with a second oxide layer, removing the first oxide layer and second oxide layer, forming a third oxide layer on the planar substrate with recessed active trench, and forming the at least one circuitous gate structure on the third oxide layer connecting at least one electronic source and drain.
    Type: Grant
    Filed: December 22, 2006
    Date of Patent: January 5, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Andrew Marshall, Gabriel George Barna
  • Publication number: 20080153218
    Abstract: A method of manufacturing a semiconductor device having recessed active trenches by providing a substrate with STI and active regions, forming a first oxide layer on the substrate, forming an nitride layer on the first oxide layer, employing a photolithographic process to create at least one recessed active trench through the first oxide layer and the nitride layer and into the substrate to create an isolation region, wherein the at least one trench is perpendicular to at least one gate structure in an active area of the substrate, layering the trench with a second oxide layer, removing the first oxide layer and second oxide layer, forming a third oxide layer on the planar substrate with recessed active trench, and forming the at least one circuitous gate structure on the third oxide layer connecting at least one electronic source and drain.
    Type: Application
    Filed: December 22, 2006
    Publication date: June 26, 2008
    Inventors: Andrew Marshall, Gabriel George Barna
  • Publication number: 20080081404
    Abstract: A method of manufacturing a semiconductor device having shallow trench isolation includes steps of forming a hard mask layer on the substrate surface, etching a trench through the hard mask, filling the trench with an isolation material, forming a recessed trench, and forming a serpentine gate structure to connect electronic sources and drains.
    Type: Application
    Filed: September 29, 2006
    Publication date: April 3, 2008
    Inventors: Gabriel George Barna, Andrew Marshall, Brian K. Kirkpatrick
  • Patent number: 7122413
    Abstract: The present invention provides a method of manufacturing a single-electron transistor device (100). The method includes forming a thinned region (110) in a silicon substrate (105), the thinned region (110) offset by a non-selected region (115). The method also includes forming at least one quantum island (145) from the thinned region (110) by subjecting the thinned region (110) to an annealing process. The non-selected region (115) is aligned with the quantum island (145) and tunnel junctions (147) are formed between the quantum island (145) and the non-selected region (115). The present invention also includes a single-electron device (200), and a method of manufacturing an integrated circuit (300) that includes a single-electron device (305).
    Type: Grant
    Filed: December 19, 2003
    Date of Patent: October 17, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Christoph Wasshuber, Gabriel George Barna, Olivier Alain Faynot