Patents by Inventor Gabriel L. Romero

Gabriel L. Romero has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9267991
    Abstract: A test pattern is encoded using a run length limited line encoding to produce an encoded block of data. The encoded block of data is sent via a channel. A plurality of bits in the received block of data that are subsequent to a maximum length run in the sent data is compared to an expected plurality of bits. A type of bit error is classified based on a mismatch between the expected plurality of bits and the plurality of bits in the received block of data.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: February 23, 2016
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Coralyn S. Gauvin, Gabriel L. Romero
  • Publication number: 20150205653
    Abstract: A test pattern is encoded using a run length limited line encoding to produce an encoded block of data. The encoded block of data is sent via a channel. A plurality of bits in the received block of data that are subsequent to a maximum length run in the sent data is compared to an expected plurality of bits. A type of bit error is classified based on a mismatch between the expected plurality of bits and the plurality of bits in the received block of data.
    Type: Application
    Filed: March 31, 2015
    Publication date: July 23, 2015
    Inventors: Coralyn S. Gauvin, Gabriel L. Romero
  • Patent number: 9021325
    Abstract: A test pattern is encoded using a run length limited line encoding to produce an encoded block of data. The encoded block of data is sent via a channel. A plurality of bits in the received block of data that are subsequent to a maximum length run in the sent data is compared to an expected plurality of bits. A type of bit error is classified based on a mismatch between the expected plurality of bits and the plurality of bits in the received block of data.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: April 28, 2015
    Assignee: LSI Corporation
    Inventors: Coralyn S. Gauvin, Gabriel L. Romero
  • Patent number: 8854983
    Abstract: Decision modules are strategically located along with various modules to route signals from either a test pattern generator or the data link layer through the various modules for performing scrambling, encoding, and serializing procedures on the signals before transmission of the signals on a serial bus. Decision modules are strategically placed along with various modules to route signals to either a test pattern checker or the data link layer through the various modules for performing descrambling, decoding, and deserializing procedures on the signals after receiving the signals from a serial bus.
    Type: Grant
    Filed: December 3, 2010
    Date of Patent: October 7, 2014
    Assignee: LSI Corporation
    Inventors: Gabriel L. Romero, Coralyn S. Gauvin
  • Publication number: 20140223270
    Abstract: A test pattern is encoded using a run length limited line encoding to produce an encoded block of data. The encoded block of data is sent via a channel. A plurality of bits in the received block of data that are subsequent to a maximum length run in the sent data is compared to an expected plurality of bits. A type of bit error is classified based on a mismatch between the expected plurality of bits and the plurality of bits in the received block of data.
    Type: Application
    Filed: February 7, 2013
    Publication date: August 7, 2014
    Applicant: LSI CORPORATION
    Inventors: Coralyn S. Gauvin, Gabriel L. Romero
  • Patent number: 8687683
    Abstract: A method for determining floating tap positions in a DFE of a receiver is disclosed. The method include providing a group of floating taps for the DFE; obtaining a baseline eye opening value for the receiver when the group of floating taps is disabled; providing a plurality of floating tap distribution configurations, each specifying a distribution configuration for the group of floating taps within the DFE; obtaining a plurality of eye opening values for the receiver, each particular eye opening value corresponding to a particular floating tap distribution configuration when the group of floating taps are distributed within the DFE according to the particular floating tap distribution configuration; comparing each of the plurality of eye opening values against the baseline eye opening value; and identifying an optimal floating tap distribution configuration based on the comparison of each of the plurality of eye opening values against the baseline eye opening value.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: April 1, 2014
    Assignee: LSI Corporation
    Inventors: John D. Gardner, Gabriel L. Romero
  • Patent number: 8566496
    Abstract: A SAS expander collects data access information associated with a nexus and determines whether a data prefetch is appropriate. The SAS expander identifies potential data blocks utilizing previous data requests of the nexus. The SAS expander issues a data request to the target for the potential data blocks. The SAS expander stores the potential data blocks within a prefetch cache for future utilization within a data read.
    Type: Grant
    Filed: December 3, 2010
    Date of Patent: October 22, 2013
    Assignee: LSI Corporation
    Inventors: Gabriel L. Romero, Frederick G. Smith
  • Publication number: 20130128946
    Abstract: A method for determining floating tap positions in a DFE of a receiver is disclosed. The method include providing a group of floating taps for the DFE; obtaining a baseline eye opening value for the receiver when the group of floating taps is disabled; providing a plurality of floating tap distribution configurations, each specifying a distribution configuration for the group of floating taps within the DFE; obtaining a plurality of eye opening values for the receiver, each particular eye opening value corresponding to a particular floating tap distribution configuration when the group of floating taps are distributed within the DFE according to the particular floating tap distribution configuration; comparing each of the plurality of eye opening values against the baseline eye opening value; and identifying an optimal floating tap distribution configuration based on the comparison of each of the plurality of eye opening values against the baseline eye opening value.
    Type: Application
    Filed: November 22, 2011
    Publication date: May 23, 2013
    Applicant: LSI CORPORATION
    Inventors: John D. Gardner, Gabriel L. Romero
  • Patent number: 8261156
    Abstract: Methods and apparatuses for correcting an error in a data stream that is coded with a line code and an error detection scheme. Information relating to the line code is used to locate at least one possible error character. At least one possible correct character to replace one or more of the at least one possible error character is then identified. Subsequently, the error detection scheme is applied to the data stream updated with one of the at least one possible correct character. If none of the at least one possible correct character results in a valid data stream, an error that is observable by a user is generated.
    Type: Grant
    Filed: September 11, 2008
    Date of Patent: September 4, 2012
    Assignee: LSI Corporation
    Inventors: Gabriel L. Romero, Frederick G. Smith
  • Publication number: 20120140840
    Abstract: Decision modules are strategically located along with various modules to route signals from either a test pattern generator or the data link layer through the various modules for performing scrambling, encoding, and serializing procedures on the signals before transmission of the signals on a serial bus. Decision modules are strategically placed along with various modules to route signals to either a test pattern checker or the data link layer through the various modules for performing descrambling, decoding, and deserializing procedures on the signals after receiving the signals from a serial bus.
    Type: Application
    Filed: December 3, 2010
    Publication date: June 7, 2012
    Applicant: LSI CORPORATION
    Inventors: Gabriel L. Romero, Coralyn S. Gauvin
  • Publication number: 20120144082
    Abstract: A SAS expander collects data access information associated with a nexus and determines whether a data prefetch is appropriate. The SAS expander identifies potential data blocks utilizing previous data requests of the nexus. The SAS expander issues a data request to the target for the potential data blocks. The SAS expander stores the potential data blocks within a prefetch cache for future utilization within a data read.
    Type: Application
    Filed: December 3, 2010
    Publication date: June 7, 2012
    Applicant: LSI CORPORATION
    Inventors: Gabriel L. Romero, Frederick G. Smith
  • Publication number: 20120042207
    Abstract: Method and structures provide for testing a SAS link during speed negotiation windows to determine success/failure in using a negotiated speed at one or more configured sets of speed options. For each device linked to a master SAS device, each possible set of speed options is configured; the device participates in a speed negotiation window operation with the current speed options configured. One or more SCSI requests are forwarded from the master device to the attached device. The SCSI requests may be non-destructive of data stored on the attached device. Results of the tests may be used to select a preferred speed for communication between the master device and that attached device. The speed options to be varied and tested may include: link speed; spread spectrum clocking for each SAS speed; type of supported spread spectrum clocking; and logical link rate in support of multiplexing.
    Type: Application
    Filed: March 26, 2007
    Publication date: February 16, 2012
    Inventors: David T. Uddenberg, Gabriel L. Romero
  • Patent number: 8116147
    Abstract: Method and structures provide for testing a SAS link during speed negotiation windows to determine success/failure in using a negotiated speed at one or more configured sets of speed options. For each device linked to a master SAS device, each possible set of speed options is configured; the device participates in a speed negotiation window operation with the current speed options configured. One or more SCSI requests are forwarded from the master device to the attached device. The SCSI requests may be non-destructive of data stored on the attached device. Results of the tests may be used to select a preferred speed for communication between the master device and that attached device. The speed options to be varied and tested may include: link speed; spread spectrum clocking for each SAS speed; type of supported spread spectrum clocking; and logical link rate in support of multiplexing.
    Type: Grant
    Filed: March 26, 2007
    Date of Patent: February 14, 2012
    Assignee: LSI Corporation
    Inventors: David T. Uddenberg, Gabriel L. Romero
  • Publication number: 20110106997
    Abstract: Methods and apparatus for interconnecting Serial Attached SCSI (SAS) or Serial Advanced Technology Attachment (SATA) devices using either an electrical communication medium or an optical communication medium. Each device includes an out of band (OOB) encoder/decoder (endec) logic component to translate between standard OOB signals used by the devices and digitally encoded OOB signals exchanged over the communication medium. Thus the devices may be coupled using either optical or electrical cabling. The digitally encoded OOB signals may also be scrambled to reduce electromagnetic interference (EMI) generated during OOB communications using the digitally encoded OOB signals. The scrambled digitally encoded OOB signals may comprise information regarding capabilities of the device that generated the underlying OOB signal. Such information may indicate to the other high speed device certain capabilities of the transmitting device—the information to be used in establishing logical connections between devices.
    Type: Application
    Filed: November 5, 2009
    Publication date: May 5, 2011
    Applicant: LSI CORPORATION
    Inventors: Gabriel L. Romero, Coralyn S. Gauvin
  • Patent number: 7936829
    Abstract: Driving multiple consecutive bits having a same logic value in a serial data stream involves driving a first bit of the multiple consecutive bits in the serial data stream at an initial voltage level, and driving at least two additional bits of the multiple consecutive bits in the serial data stream at voltage levels stepped down from the initial voltage level.
    Type: Grant
    Filed: October 22, 2004
    Date of Patent: May 3, 2011
    Assignee: LSI Corporation
    Inventors: Gabriel L. Romero, Frederick G. Smith, Brian E. Burdick
  • Patent number: 7805554
    Abstract: Method and structures provide for testing a SAS link in association with participating in training windows to determine success/failure in using a negotiated speed using one or more configured sets of transceiver training options. For each device linked to a master SAS device, each possible set of transceiver training options is configured and one or more SCSI requests are forwarded from the master device to the attached device. The SCSI requests may be non-destructive of data stored on the attached device. Results of the tests may be used to select a preferred set of transceiver training options for communication between the master device and that attached device. The transceiver training options to be varied and tested may include: amplitude, slew rate, de-emphasis, and spread spectrum clocking.
    Type: Grant
    Filed: March 26, 2007
    Date of Patent: September 28, 2010
    Assignee: LSI Corporation
    Inventors: David T. Uddenberg, Gabriel L. Romero
  • Patent number: 7774669
    Abstract: The present invention provides systems, devices and methods for generating user-defined test patterns within serial controller to facilitate signal testing and verification. These user-defined test patterns may be generated to more accurately reflect the actual traffic of a device-under-test or system, as well as allow a test engineer to more accurately test the boundaries of the device or system. In various embodiments of the invention, a programmable patterns generator is provided for generating user-defined test patterns that may be used during a testing procedure. This programmable pattern generator allows a user to define a particular test pattern by providing bit-by-bit test values, by defining a combination of canned sequences, or by supplementing one or more canned sequences with additional test bits.
    Type: Grant
    Filed: June 11, 2007
    Date of Patent: August 10, 2010
    Assignee: LSI Corporation
    Inventors: Gabriel L. Romero, Coralyn S. Gauvin
  • Publication number: 20100064192
    Abstract: Methods and apparatuses for correcting an error in a data stream that is coded with a line code and an error detection scheme. Information relating to the line code is used to locate at least one possible error character. At least one possible correct character to replace one or more of the at least one possible error character is then identified. Subsequently, the error detection scheme is applied to the data stream updated with one of the at least one possible correct character. If none of the at least one possible correct character results in a valid data stream, an error that is observable by a user is generated.
    Type: Application
    Filed: September 11, 2008
    Publication date: March 11, 2010
    Inventors: Gabriel L. Romero, Frederick G. Smith
  • Publication number: 20080307283
    Abstract: The present invention provides systems, devices and methods for generating user-defined test patterns within serial controller to facilitate signal testing and verification. These user-defined test patterns may be generated to more accurately reflect the actual traffic of a device-under-test or system, as well as allow a test engineer to more accurately test the boundaries of the device or system. In various embodiments of the invention, a programmable patterns generator is provided for generating user-defined test patterns that may be used during a testing procedure. This programmable pattern generator allows a user to define a particular test pattern by providing bit-by-bit test values, by defining a combination of canned sequences, or by supplementing one or more canned sequences with additional test bits.
    Type: Application
    Filed: June 11, 2007
    Publication date: December 11, 2008
    Inventors: Gabriel L. Romero, Coralyn S. Gauvin
  • Publication number: 20080244100
    Abstract: Method and structures provide for testing a SAS link in association with participating in training windows to determine success/failure in using a negotiated speed using one or more configured sets of transceiver training options. For each device linked to a master SAS device, each possible set of transceiver training options is configured and one or more SCSI requests are forwarded from the master device to the attached device. The SCSI requests may be non-destructive of data stored on the attached device. Results of the tests may be used to select a preferred set of transceiver training options for communication between the master device and that attached device. The transceiver training options to be varied and tested may include: amplitude, slew rate, de-emphasis, and spread spectrum clocking.
    Type: Application
    Filed: March 26, 2007
    Publication date: October 2, 2008
    Inventors: David T. Uddenberg, Gabriel L. Romero