Abstract: Systems and methods for model-driven system integration on a ventilator comprise a modeled exhalation flow. Ventilator flow sensors contain components that are easily damaged or impacted and have high rates of failure. Knowledge failure frequency and type may help determine when to replace, clean, or calibrate a flow sensor. A modeled exhalation flow may be trained for a ventilator. Additionally, the modeled exhalation flow may be compared to a flow sensor flow to determine a specific failure. Additionally or alternatively, the modeled exhalation flow may supplement, weight, or replace a faulty flow sensor measurement. These systems and methods may assist in identifying an inaccurate flow sensor measurement and/or providing a more accurate modeled flow estimate, thus increasing accuracy in patient-ventilator interactions.

Abstract: Embodiments of the invention are directed to systems and methods for conducting a transaction utilizing a cryptocurrency. The user may fund a cryptocurrency account with his pre-existing cryptocurrency. An issuer may purchase cryptocurrency within a cryptocurrency exchange. The user may then utilize a payment device (e.g., a Crypto Debit Card) that is associated with a cryptocurrency balance to conduct a transaction with a merchant for goods and/or services. An authorization request message may be transmitted to the authorizing entity computer. The authorizing entity computer may determine a cryptocurrency amount corresponding to the fiat currency transaction amount of the authorization request message. A sell request message may be transmitted to an exchange that facilitates the sale of the cryptocurrency amount.

Abstract: Electrochemical sensors have great promise for point-of-care and in vivo measurement of medically relevant molecules. However, the need for calibrating individual sensors limits the practical applicability of these sensing platforms. The invention provides a novel method of operating electrochemical sensors which obviates the need to calibrate individual sensors against a sample of known concentration. The invention exploits the frequency dependence of electrochemical output signals and the dependence of output signals on the inherent electron transfer kinetics of a selected sensor design. By use of signals generated at a nonresponsive frequency, a normalizing output value is generated that accounts for sensor-to-sensor variation and which enables an accurate calculation of target concentration. The scope of the invention also includes pre-calibrated sensors that may be utilized without calibration steps.

Abstract: A hybrid single-limb patient circuit coupled to an inspiratory port and an expiratory port of a ventilator. The hybrid single-limb patient circuit may include a check valve positioned to direct breathing gases supplied from the inspiratory port in a single direction; a manifold pneumatically coupled to the check valve; a dual-purpose single limb, pneumatically coupled to the manifold and the non-invasive patient interface, to carry breathing gases to the non-invasive patient interface and carry exhaled gases from the non-invasive patient interface; and an exhalation tubing segment, pneumatically coupled to the manifold and the expiratory port, to carry the exhaled gases from the manifold to the expiratory port.

Abstract: Provided are a method, a system and an electronic device for implementing flexible graphics enhancement and execution. For example, a flexible graphics enhancement and execution component can be an integrated element of a graphics application programming interface (API) that allows a visual effect of style to be added to the 3D graphics rendered from a mobile game. The techniques can include intercepting an initial function call, where the initial function call is associated with a graphics API rendering an image for an application. Then, a custom function can be automatically generated, based on the intercepted initial function call. A pointer associated with the generated custom function can be returned to the application, where the custom function modifies an output from the graphics API to add a visual effect to a three-dimensional (3D) rendered image of the application. The graphics API can be an Open Graphics Library (OpenGL) API.

Abstract: Technology for an Information Centric Networking gateway (ICN-GW) operable to modify an ICN message received from a user equipment (UE) in a Fifth Generation (5G) cellular network is disclosed. The ICN-GW can decode the ICN message received from the UE via a Next 5 Generation NodeB (gNB) and an ICN point of attachment (ICNPoA). The ICN-GW can modify the ICN message to produce a modified ICN message. The ICN-GW can encode the modified ICN message to route the modified ICN message to a data network.

Abstract: A method for network coding at a packet data convergence protocol (PDCP) layer by a next-generation NodeB (gNB) includes selecting a coding coefficient from a location in a Vandermonde matrix. The method includes setting an identifier value identifying the location in the Vandermonde matrix corresponding to the selected coding coefficient. The method includes encoding one or more packets each comprising a PDCP data unit. The encoding of at least one of the one or more packets includes applying a function to data in the packet, the function including the coding coefficient. The method includes generating a message comprising the at least one encoded packet. The method includes transmitting the message to a user equipment (UE).

Abstract: In an embodiment, an apparatus includes a memory controller configured to control a plurality of daisy chained memory components connected over a daisy chained bus. The daisy chained bus includes a direct connection from the transmit interface of the memory controller to a receive interface of an initial memory component, and a daisy chain connection from a transmit interface of the initial memory component to a receive interface of a next memory component. A bus extends from a transmit interface of a last memory component directly to a receive interface of the memory controller.

Abstract: A serial interface device includes multiple serial link connections that receive at least address values and at least one error detection code (EDC) on different serial link connections, the EDC generated from at least the address values, the serial link connections for the address values and EDC operated separately from one another; and multiple output serial links, at least a first one of the output serial links outputting data values read from memory locations corresponding to the address values, and at least a second one of the output serial links different from and operated separately from the first one outputting EDC values generated for the data values read from the memory locations.

Abstract: An output driver circuit can include at least a first driver transistor having a source-drain path coupled between a first power supply node and an output node. A first variable current supply can generate a current having at least one component that is inversely proportional to a power supply voltage. A first driver switch element can be coupled in series with the first variable current supply between a gate of the at least first driver transistor and a second power supply node.

Abstract: An apparatus having a plurality of power supply domains and a plurality of logic components. Each of the plurality of logic components residing within a different one of the plurality of power supply domains. Each of the plurality of logic components is configured to operate with a corresponding clock signal within a respective one of the plurality of power supply domains.

Abstract: Disclosed is a circuit and method to program the starting phase of the spread spectrum of a clock output. The circuit includes a plurality of phase locked loop (PLL) circuits for generating a plurality of spread spectrum waveforms. The circuit also includes a spread control circuit for controlling each of the plurality of PLL circuits in accordance with a plurality of respective spread profiles. The spread profiles are configured to vary a starting phase of each spread spectrum waveform such that a total energy of each spread spectrum waveform is out of phase with other spread spectrum waveforms.

Abstract: In an embodiment, an apparatus includes a memory controller configured to control first and second memory components. A point-to-point data bus configured to pass data between the memory controller and the memory components may include a direct connection from each memory component to the memory controller. A daisy chained address bus configured to pass commands between the memory controller and the memory components may include a direct connection from the first memory component to the memory controller and a daisy chain connection from the first memory component to the second memory component.

Abstract: In an embodiment, an apparatus includes a memory controller configured to control a plurality of daisy chained memory components connected over a daisy chained bus. The daisy chained bus includes a direct connection from the transmit interface of the memory controller to a receive interface of an initial memory component, and a daisy chain connection from a transmit interface of the initial memory component to a receive interface of a next memory component. A bus extends from a transmit interface of a last memory component directly to a receive interface of the memory controller.

Abstract: An apparatus having a plurality of power supply domains and a plurality of logic components. Each of the plurality of logic components residing within a different one of the plurality of power supply domains. Each of the plurality of logic components is configured to operate with a corresponding clock signal within a respective one of the plurality of power supply domains.

Abstract: An apparatus having a plurality of power supply domains and a plurality of logic components. Each of the plurality of logic components residing within a different one of the plurality of power supply domains. Each of the plurality of logic components is configured to operate with a corresponding clock signal within a respective one of the plurality of power supply domains.

Abstract: An output driver circuit can include at least a first driver transistor having a source-drain path coupled between a first power supply node and an output node. A first variable current supply can generate a current having at least one component that is inversely proportional to a power supply voltage. A first driver switch element can be coupled in series with the first variable current supply between a gate of the at least first driver transistor and a second power supply node.

Abstract: A serial interface device may include a plurality of serial link connections that receive at least address values and at least one error detection code (EDC) on different serial link connections, the EDC generated from at least the address values.

Abstract: A test circuit, system, and method are provided herein for testing one or more circuit components arranged upon a monolithic substrate. According to one embodiment, the system may include a test circuit and one or more circuit components, all of which are arranged upon the same monolithic substrate. In general, the test circuit may be configured for: (i) receiving an input signal at an input frequency, (ii) generating a test signal by modulating a phase of the input signal in accordance with a periodic signal, and (iii) supplying either the input signal or the test signal to the one or more integrated circuits, based on a control signal supplied to the test circuit. More specifically, the test circuit may be used to determine the jitter and/or duty cycle distortion (DCD) tolerance of any system component without changing the frequency of the clock signal supplied to the component or injecting noise into the clock recovery system.

Abstract: In an embodiment, an apparatus includes a memory controller configured to control first and second memory components. A point-to-point data bus configured to pass data between the memory controller and the memory components may include a direct connection from each memory component to the memory controller. A daisy chained address bus configured to pass commands between the memory controller and the memory components may include a direct connection from the first memory component to the memory controller and a daisy chain connection from the first memory component to the second memory component.