Abstract: A circuit and method are provided herein for monitoring the status of a clock signal. In general, the method may include supplying a pair of clock signals to a clock monitor circuit, which is configured for monitoring a status of one clock signal relative to the other. The status indicates whether the frequency of the one clock signal is faster, slower or substantially equal to the frequency of the other clock signal. Once determined, the status may be stored as a bit pattern within a status register, which is operatively coupled to the clock monitor circuit. This enables the status to be read by detecting a logic state of one or more bits within the status register.

Abstract: Circuits and methods are provided herein for monitoring the integrity of a power supply, the circuits and methods providing additional resources/information for diagnosing a cause behind a reset signal, and in some cases, a reason behind a power failure. A first method described herein provides exemplary steps for monitoring a level of a power supply voltage supplied to one or more system components. A second method describes exemplary steps for monitoring an electrical connection between the power supply (or ground supply) and one or more supply pins. Each of the methods involves monitoring a state of one or more bits stored, e.g., within a status register. The methods may be used separately, or in conjunction with one another, for detecting the occurrence of a power abnormality.

Abstract: A system and method are provided herein for monitoring the integrity of a power supply by monitoring a level of the power supply voltage supplied to one or more system components. The method, as described herein, includes setting a bit in a status register after the power supply level reaches a threshold level, and monitoring a state of the bit to determine if the power supply level has dropped below the threshold level. For example, the method may determine that the power supply level has dropped below the threshold level if the state of the bit changes from a set bit to a cleared bit. In addition, the system and method described herein may be used for detecting the occurrence of a power abnormality by providing additional resources/information about a power related event.

Abstract: A parallel data interface and method is provided herein, which adjusts a timing relationship of a clock signal to not only minimize clock skew, but to also compensate for noise components that may affect one or more paths of a parallel data bus. In some embodiments, the parallel data interface includes a first phase generator coupled to generate a first plurality of time delay pulses, and a first phase selector adapted to select one of the first plurality of time delay pulses to adjust the timing of a clock signal to sample each and every one of the plurality of data signals between minimum setup and hold time thresholds. In some embodiments, the parallel data interface includes a second phase generator coupled to generate a second plurality of time delay pulses, and a second phase selector adapted to select one of the second plurality of time delay pulses to adjust the timing of the clock signal to output the plurality of data signals from the data interface at least an amount of time (i.e.

Abstract: A framing circuit, which frames bytes of data received from a serial data bit stream, prevents a short byte clock pulse from being formed when the byte clock signal, which identifies the beginning of each frame, is reset. The framing circuit utilizes a comparison stage to output a match signal each time an n-bit data bit pattern matches a programmable predetermined framing pattern, and to delay each n-bit pattern a delay time. The framing circuit also utilizes a counter to produce the byte clock signal, and a delay circuit to freeze the output of the counter for a predetermined delay time each time the match signal is output. The delay circuit also resets the byte clock signal so that the reset byte clock signal coincides with the output of the delayed data bit pattern. By freezing the output of the counter for a predetermined time, the width of the resulting pulse is lengthened.

Abstract: A phase-locked loop having a phase error processor (PEP) circuit in which a phase error is provided to the PEP circuit in the form of a first pulse stream comprising pulses of a width dictated by the phase error between the incoming data and a local clock and a second pulse stream comprising pulses of a reference width. The circuit includes two integrators having outputs coupled to first and second inputs of a comparator, respectively. Switches couple the first pulse stream to the input of one integrator and the second pulse stream to the input of the other integrator during a first time window and reverse the connections during a second time window. The switches are controlled by a SWAP signal which alternates state at regular intervals. The output of the comparator is exclusive-ORed with the SWAP signal in order to invert the comparator output signal every other window so as to average any input offset error of the comparator or offset due to mismatch of the integrators evenly between the two pulse streams.

Abstract: A symbol-wide elasticity buffer for a receive/transmit station within an asynchronous data transmission network provides both for reframing after each packet and for the handling of a continuous line state symbol for a period longer than the allowed packet size. According to one aspect of the invention, the elasticity buffer is divided into a START section and a CONTINUATION section. The buffer's write pointer will not enter the CONTINUATION section until the read pointer is directed to the first of the multiple, sequential registers comprising the START section. The read pointer must sequentially read the START section registers before entering the CONTINUATION section. Once the write pointer or read pointer leaves the START section, it can only reenter the START section upon receipt of a start delimiter signal. When the write pointer or the read pointer reaches the last register in the CONTINUATION section, it is automatically routed back to the first CONTINUATION section register.

Abstract: A clock distribution device (CDD) (100) is used in a concentrator (200,300) to distribute multiple bits of serial data (208) in parallel across back plane boards (Board A, B, N. NN) as a byte-wide data signal (214). Each back plane board (Board A, B, N, NN) has a CDD (100). One back plane board (Board A) has a master oscillator (120) which generates a local low frequency reference clock signal (212). The reference clock signal (212) is distributed to all of the back plane boards (Board A, B, N, NN) where each board's CDD (100) uses the reference clock signal (212) to generate a high frequency clock signal (TXCLK) and a plurality of local phase separated clock signals (LBC1-LBC5).

Abstract: A method and apparatus for synchronizing the cascaded, multi-channel transmission of a plurality of data characters is provided. Each sequence of data characters preceded by a start delimiter. Each transmission channel provides transmitted data frames to an associated elasticity buffer. As each channel detects a start delimiter, it asserts a begin-request signal that acknowledges detection of the start delimiter. When all channels have detected a start delimiter, a read-start signal is asserted to simultaneously advance the read pointer of each elasticity buffer. In this manner, each elasticity buffer initiates a sunchronized read for local use or retransmission of the multi-channel data.

Abstract: An exclusive-or circuit which is extremely fast, uses lower power and fewer components, and is easier to manufacture than prior art circuits is achieved in a circuit which uses only a single reference voltage potential (shown as positive) in the portion of the circuit which generates exclusive-nor logic, and uses a feedback transistor to prevent saturation of a switching transistor. In the off state of the switching transistor, the single reference potential causes the base to be several saturation potentials above ground. In the on state, the feedback transistor reduces the base current. Thus the voltage swing between on and off states is less than in prior art circuits. In addition, the logic from many input signals can be combined to create a single exclusive-nor signal before buffering to an exclusive-or signal at the output terminal.