Abstract: Technical solutions are described for a supervisory processor to pass an out-of-band communication to a target processor in a multiprocessor system. For example, a first processor in a multi-processor system includes a register configured to store a command from a second processor of the multi-processor system, and to store a response to the command from the second processor. The first processor determines that the second processor has issued the command for execution by the first processor based on a first portion of the register being set to a first state, which is a predetermined state. The first processor also, responsively, reads the command from the second processor by parsing a second portion of the register. The first processor includes executes the command and stores the response for the command in the register.

Abstract: A system for managing one or more queues in a multi-processor environment includes a shared memory configured to be accessed by a plurality of processing elements, and a queue manager configured to control a queue in the shared memory, the queue manager storing dynamically configurable queue parameters including an operation address associated with the queue, a number of queue elements and a size of each queue element. The queue manager is configured to intercept a message from a processing element, the message directed to the shared memory and specifying the operation address, calculate an address of a location in the shared memory corresponding to one or more available queue elements, the calculating performed based on the operation address, the number of queue elements, and the size of each queue element, and perform one or more queuing operations on the queue based on the calculated address.

Abstract: A system for managing one or more queues in a multi-processor environment includes a shared memory configured to be accessed by a plurality of processing elements, and a queue manager configured to control a queue in the shared memory, the queue manager storing dynamically configurable queue parameters including an operation address associated with the queue, a number of queue elements and a size of each queue element. The queue manager is configured to intercept a message from a processing element, the message directed to the shared memory and specifying the operation address, calculate an address of a location in the shared memory corresponding to one or more available queue elements, the calculating performed based on the operation address, the number of queue elements, and the size of each queue element, and perform one or more queuing operations on the queue based on the calculated address.

Abstract: A system for managing one or more queues in a multi-processor environment includes a queue manager disposed in communication with a plurality of processors and a memory shared by the plurality of processors, and a queue configured to be controlled by the queue manager, the queue including independent and discrete queue elements and having a starting location specified by a base address, the queue manager having one or more dynamically configurable parameters, the one or more dynamically configurable parameters including a size of each of the queue elements. The queue manager is configured to perform receiving a message from a processor of the plurality of processors, the message including an operation address specifying a fixed storage location in the memory and a request related to accessing the memory, selecting the queue based on the operation address, and performing a queuing operation on the queue based on the request.

Abstract: A system for managing one or more queues in a multi-processor environment includes a shared memory configured to be accessed by a plurality of processing elements, and a queue manager configured to control a queue in the shared memory, the queue manager storing dynamically configurable queue parameters including an operation address associated with the queue, a number of queue elements and a size of each queue element. The queue manager is configured to intercept a message from a processing element, the message directed to the shared memory and specifying the operation address, calculate an address of a location in the shared memory corresponding to one or more available queue elements, the calculating performed based on the operation address, the number of queue elements, and the size of each queue element, and perform one or more queuing operations on the queue based on the calculated address.

Abstract: A system for managing one or more queues in a multi-processor environment includes a shared memory configured to be accessed by a plurality of processing elements, and a queue manager configured to control a queue in the shared memory, the queue manager storing dynamically configurable queue parameters including an operation address associated with the queue, a number of queue elements and a size of each queue element. The queue manager is configured to intercept a message from a processing element, the message directed to the shared memory and specifying the operation address, calculate an address of a location in the shared memory corresponding to one or more available queue elements, the calculating performed based on the operation address, the number of queue elements, and the size of each queue element, and perform one or more queuing operations on the queue based on the calculated address.

Abstract: A system for managing one or more queues in a multi-processor environment includes a queue manager disposed in communication with a plurality of processors and a memory shared by the plurality of processors, and a queue configured to be controlled by the queue manager, the queue including independent and discrete queue elements and having a starting location specified by a base address, the queue manager having one or more dynamically configurable parameters, the one or more dynamically configurable parameters including a size of each of the queue elements. The queue manager is configured to perform receiving a message from a processor of the plurality of processors, the message including an operation address specifying a fixed storage location in the memory and a request related to accessing the memory, selecting the queue based on the operation address, and performing a queuing operation on the queue based on the request.

Abstract: Technical solutions are described for a supervisory processor to pass an out-of-band communication to a target processor in a multiprocessor system. For example, a first processor in a multi-processor system includes a register configured to store a command from a second processor of the multi-processor system, and to store a response to the command from the second processor. The first processor determines that the second processor has issued the command for execution by the first processor based on a first portion of the register being set to a first state, which is a predetermined state. The first processor also, responsively, reads the command from the second processor by parsing a second portion of the register. The first processor includes executes the command and stores the response for the command in the register.

Abstract: A system to improve data packet routing in a data processing device may include a plurality of functional modules, and communication buses connecting the functional modules. The system may also include a flow control mechanism in which command packets that traverse the communication buses are each assigned their own channel with their own pool of credits. The system may further include a switch to route data packets on the communication buses from one of the functional modules to any other of the functional modules based upon the credits. In addition, any of the functional modules without credits to send the data packets on a particular channel may send a message to have the switch perform a route test.

Abstract: Debugging microcode is facilitated by a hardware assist that takes over from the microcode the basic management of handling the data for a trace entry, thereby reducing the load on the microcode to a single micro-instruction per trace operation and thereby permitting more trace points to be included in the microcode shipped to the field.