Patents by Inventor Gabriel Maier

Gabriel Maier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • HANDLING THIN WAFER DURING CHIP MANUFACTURE
    Publication number: 20180233470
    Abstract: A manufacturing method is provided which comprises forming recesses in a front side of a wafer, connecting a first temporary holding body to the front side of the recessed wafer, thereafter thinning the wafer from a back side, connecting a second temporary holding body to the back side, and thereafter removing the first temporary holding body.
    Type: Application
    Filed: February 15, 2018
    Publication date: August 16, 2018
    Applicant: Infineon Technologies AG
    Inventors: Thomas Killer, Markus Brunnbauer, Marina Janker, Adolf Koller, Gabriel Maier, Andreas Mueller-Hipper, Andreas Stueckjuergen, Christine Thoms
  • Methods for manufacturing a chip arrangement, methods for manufacturing a chip package, a chip package and chip arrangements
    Patent number: 9576875
    Abstract: A method for manufacturing a chip arrangement is provided, the method including: forming a hole in a carrier including at least one chip, wherein forming a hole in the carrier includes: selectively removing carrier material, thereby forming a cavity in the carrier, forming passivation material over one or more cavity walls exposed by the selective removal of the carrier material; selectively removing a portion of the passivation material and further carrier material exposed by the selective removal of the passivation material, wherein a further portion of the passivation material remains over at least one cavity side wall; the method further including subsequently forming a layer over the further portion of passivation material remaining over the at least one cavity side wall.
    Type: Grant
    Filed: January 7, 2015
    Date of Patent: February 21, 2017
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Reinhard Hess, Katharina Umminger, Gabriel Maier, Markus Menath, Gunther Mackh, Hannes Eder, Alexander Heinrich
  • METHODS FOR MANUFACTURING A CHIP ARRANGEMENT, METHODS FOR MANUFACTURING A CHIP PACKAGE, A CHIP PACKAGE AND CHIP ARRANGEMENTS
    Publication number: 20150115417
    Abstract: A method for manufacturing a chip arrangement is provided, the method including: forming a hole in a carrier including at least one chip, wherein forming a hole in the carrier includes: selectively removing carrier material, thereby forming a cavity in the carrier, forming passivation material over one or more cavity walls exposed by the selective removal of the carrier material; selectively removing a portion of the passivation material and further carrier material exposed by the selective removal of the passivation material, wherein a further portion of the passivation material remains over at least one cavity side wall; the method further including subsequently forming a layer over the further portion of passivation material remaining over the at least one cavity side wall.
    Type: Application
    Filed: January 7, 2015
    Publication date: April 30, 2015
    Inventors: Reinhard HESS, Katharina UMMINGER, Gabriel MAIER, Markus MENATH, Gunther MACKH, Hannes EDER, Alexander HEINRICH
  • Methods for manufacturing a chip arrangement, methods for manufacturing a chip package, a chip package and chip arrangements
    Patent number: 8951915
    Abstract: A method for manufacturing a chip arrangement is provided, the method including: forming a hole in a carrier including at least one chip, wherein forming a hole in the carrier includes: selectively removing carrier material, thereby forming a cavity in the carrier, forming passivation material over one or more cavity walls exposed by the selective removal of the carrier material; selectively removing a portion of the passivation material and further carrier material exposed by the selective removal of the passivation material, wherein a further portion of the passivation material remains over at least one cavity side wall; the method further including subsequently forming a layer over the further portion of passivation material remaining over the at least one cavity side wall.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: February 10, 2015
    Assignee: Infineon Technologies AG
    Inventors: Reinhard Hess, Katharina Umminger, Gabriel Maier, Markus Menath, Gunther Mackh, Hannes Eder, Alexander Heinrich
  • Methods for manufacturing a chip arrangement, methods for manufacturing a chip package, a chip package and chip arrangements
    Publication number: 20140070376
    Abstract: A method for manufacturing a chip arrangement is provided, the method including: forming a hole in a carrier including at least one chip, wherein forming a hole in the carrier includes: selectively removing carrier material, thereby forming a cavity in the carrier, forming passivation material over one or more cavity walls exposed by the selective removal of the carrier material; selectively removing a portion of the passivation material and further carrier material exposed by the selective removal of the passivation material, wherein a further portion of the passivation material remains over at least one cavity side wall; the method further including subsequently forming a layer over the further portion of passivation material remaining over the at least one cavity side wall.
    Type: Application
    Filed: September 11, 2012
    Publication date: March 13, 2014
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Reinhard Hess, Katharina Umminger, Gabriel Maier, Markus Menath, Gunther Mackh, Hannes Eder, Alexander Heinrich