Abstract: Resistive random-access memories (ReRAMs) suffer from a read disturb phenomenon that results from the fact that the read and programming operations use the same voltage polarity, though at different voltages. After a number of reads, which may be small or large depending on the characteristic of each cell, outlier cells distinctly switch after a much small number of reads than other cells. Accordingly, a process comprising SET or RESET operation of the ReRAM cells, is followed by a CLEAN operation. The CLEAN operation involves application of a cleaning voltage that is greater than the read voltage and lesser than the programming voltage. Subsequently, a READ operation is performed to identify those ReRAM cells that have switched from their expected state. In an embodiment a reprogramming operation takes place to fix the resistive filament of the ReRAM cells identified to suffer from the read disturb.

Abstract: A memory device (100) comprising an array of memory cells (102.1-102.4) each comprising M memory elements (106) and a switch (104), the memory cells being addressed by word lines (108), source lines (112) and bit lines (110), wherein: a first conduction electrode of each switch is coupled to a first electrode of each of the memory elements of a single one of the memory cells; each word line is coupled to a control electrode of each switch of a single and same column of memory cells; each source line is coupled to a second conduction electrode of each switch of a single and same row of memory cells; each bit line is coupled to a second electrode of one of the memory elements of each memory cell of a single and same column of memory cells.

Abstract: A method (100) of programming a high resistive state of a memory element (Stck) part of a resistive random access memory (MEM), the method (100) comprising: an initial step (S110) of writing the high resistive state of the memory element (Stck); and a reconditioning step (S140) following the initial step (S110) of writing the high resistive state (HRS), the reconditioning step (S140) comprising at least one cycle of operations comprising, in this order: a reconditioning set operation (SETrec) that consists in running a reconditioning set current (Irec.set) through the memory element (Stck), the reconditioning set current (Irec.set) having an absolute value lower than the nominal programming current (Ip.set); and a reconditioning reset operation (RESET) that consists in running a reconditioning reset current (Ireset) through the memory element (Stck).

Abstract: A resistive stack (Stck) for a resistive random-access memory cell, the resistive stack comprising: a first electrode (E11); a second electrode (E12); a dielectric layer (Diel) interposed between the first electrode (E11) and the second electrode (E12), the dielectric layer comprising: a first dielectric layer (Diel1) formed from a first transition metal oxide; a second dielectric layer (Diel2) formed from a second transition metal oxide different from the first transition metal oxide; and a diffusion barrier layer (DiffBar) interposed between the first dielectric layer (Diel1) and the second dielectric layer (Diel2), and formed from a material having a barrier property with regard to oxygen vacancies, that is higher than barrier properties with regard to oxygen vacancies of the first transition metal oxide and the second transition metal oxide.

Abstract: A method for manufacturing an OxRAM resistive memory cell, includes forming a TiN lower electrode, firstly implanting Si atoms into the lower electrode with a first implantation dose and a first implantation acceleration voltage, the first implantation dose being strictly positive and strictly lower than 0.7·1014 cm?2, secondly implanting Si atoms into the lower electrode with a second implantation dose and a second implantation acceleration voltage strictly greater than the first implantation acceleration voltage, the second implantation dose being strictly positive and strictly lower than 0.6·1014 cm?2, the first and second acceleration voltages being selected to have an implantation profile following the first and second implantations having a maximum Si concentration at a depth of between 1 and 3 nm from the upper surface of the lower electrode, depositing an active layer onto the lower electrode implanted, depositing an upper electrode onto the active layer.

Abstract: A memory includes at least one resistive memory cell and a write device. The memory cell includes a memory element having at least a highly resistive state and a lowly resistive state, and a selector arranged in series with the memory element, the selector being electrically conductive when a voltage greater than a given threshold voltage is applied to the selector. The write device includes at least one write capacitor and one charging device, and is configured to charge the write capacitor and then to connect it to the memory cell to program that cell.

Abstract: A method for manufacturing an OxRAM type resistive memory cell including a silicon oxide layer, the method including determining manufacturing parameter values enabling the resistive memory cell to have an initial resistance between 107? and 3·109?; and forming on a substrate a stack successively including a first electrode, the silicon oxide layer and a second electrode, by applying the manufacturing parameter values.

Abstract: An OxRAM resistive memory cell includes a lower electrode, an upper electrode, and an active layer which extends between the lower electrode and the upper electrode. The active layer includes a layer of a first electrically insulating oxide, wherein an electrically conductive filament can be formed, then subsequently broken and reformed several times successively. The upper electrode includes a reservoir layer, capable of receiving oxygen, which includes an upper part made of a metal and a lower part made of a second oxide, the second oxide being an oxide of the metal and including a proportion of oxygen such that the second oxide is electrically conductive.

Abstract: A method for manufacturing an OxRAM resistive memory cell, includes forming a TiN lower electrode, firstly implanting Si atoms into the lower electrode with a first implantation dose and a first implantation acceleration voltage, the first implantation dose being strictly positive and strictly lower than 0.7·1014 cm?2, secondly implanting Si atoms into the lower electrode with a second implantation dose and a second implantation acceleration voltage strictly greater than the first implantation acceleration voltage, the second implantation dose being strictly positive and strictly lower than 0.6·1014 cm?2, the first and second acceleration voltages being selected to have an implantation profile following the first and second implantations having a maximum Si concentration at a depth of between 1 and 3 nm from the upper surface of the lower electrode, depositing an active layer onto the lower electrode implanted, depositing an upper electrode onto the active layer.

Abstract: The present disclosure relates to a method for estimating the resistive state to which a cell of a memory is programmed, the method comprising: a) a first measurement, by a measurement circuit coupled to the cell, of a first value representative of the resistance of the cell; b) at least one second measurement of at least one second value representative of the resistance of the cell; c) comparison, by a comparison circuit, of the first and the at least one second values representative of the resistance; and d) based on the comparison, estimate of the resistive state of the cell, the estimate being either of a high resistance state if the at least one second representative value has an increase relative to the first representative value, or of a low resistance state if the at least one second value has a decrease relative to the first representative value.

Abstract: An assembly of non-volatile resistive memories associated with a selector, includes a selector layer and an upper electrode; a first memory stack including a first active layer, extending against a part of a lateral surface of the upper electrode; a second memory stack including a second active layer, extending against another part of the lateral surface of the upper electrode; the upper electrode being common to the first and the second memory stack.

Abstract: An assembly includes at least two non-volatile resistive memories arranged electrically in parallel to one another and each being electrically connected in series to a selector layer respectively forming at least two selectors, each one assigned to one of the memories, the assembly including two upper electrodes which both extend over the selector layer and which are electrically insulated from each other, one of the resistive memories extending against a lateral surface of the first upper electrode and another of the resistive memories extending against a lateral surface of the second upper electrode.

Abstract: An assembly includes at least two selectors arranged electrically in parallel to one another and each being electrically connected in series to a memory layer forming at least two distinct non-volatile resistive memories each associated, respectively, with one of the two selectors, the assembly including two upper electrodes which both extend over the memory layer and which are electrically insulated from each other, one of the selectors extending against a lateral surface of the first upper electrode and another of the selectors extending against a lateral surface of the second upper electrode.

Abstract: A method for determining a value of a manufacturing parameter of a resistive memory cell, the resistive memory cell including a stack of layers, includes providing reference memory cells corresponding to technological alternatives of the stack of layers; measuring for each reference memory cell an initial resistance value; determining for each reference memory cell a programming parameter value selected from among the resistance in a high resistance state and the programming window; establishing a relationship between the programming parameter and the initial resistance from the initial resistance values and the programming parameter values; and determining the manufacturing parameter value for which the programming parameter is greater than or equal to a target value, from the relationship between the programming parameter and the initial resistance and from a dependency relationship between the initial resistance and the manufacturing parameter.

Abstract: A method for resetting an array of RAM cells by applying a sequence of N reset operations, the method including at a first reset operation, defining a first reset technique and performing the first reset operation; at a j-th reset operation of a N?1 subsequent reset operations, j being an integer between 2 and N, if a correction yield of the reset technique used at the (j?1)-th reset operation fulfils a predefined condition, applying the reset technique used at the (j?1)-th reset operation to perform the j-th reset operation, if the correction yield does not fulfil the predefined condition, defining a new reset technique and applying the new reset technique to perform the j-th reset operation, the correction yield being a cumulative correction yield or a relative correction yield, the correction yield for the N reset operations being measured prior to the first reset operation.

Abstract: A method for programming at least one resistive memory cell of an array of resistive memory cells, includes a sequence of N programming cycles, N being an integer greater than or equal to 2, each programming cycle including a set procedure and a reset procedure, each set procedure including the application of a set technique chosen among a plurality of set techniques, the method including acquiring a bit error ratio value corresponding to each programming cycle for each set technique; and at each programming cycle, applying the set technique having the lowest bit error ratio value corresponding to the programming cycle.

Abstract: A memory includes a matrix of resistive memory cells and an interfacing device to interface the matrix, the interfacing device including at least a conversion capacitor, an electric source, a first switch and a second switch, the interfacing device being configured to: a) connect the conversion capacitor to the source by the second switch to charge the conversion capacitor, then, b) disconnect the conversion capacitor from the source and connect the conversion capacitor to the matrix to achieve a conversion between, on the one hand, a resistive state of one of the memory cells of the matrix, and, on the other hand, a state of charge of the conversion capacitor.

Abstract: A method for resetting an array of Resistive Memory cells by applying a sequence of N reset operations, each reset operation including the application of a reset technique, the method including, at the first reset operation, performing the first reset operation by applying the reset technique having the highest relative correction yield; at the j-th reset operation of the N?1 subsequent reset operations, j being an integer number between 2 and N, defining a reset technique to be used at the j-th reset operation and performing the j-th reset operation.

Abstract: A method for calculating a MAC operation is performed by a memory, in particular in the neuromorphic calculation field. It allows performing the scalar product between an activation vector whose elements are binary with a vector of synaptic coefficients, quantised over M>2 levels. The calculation comprises a first phase, in which M?1 reading voltages Vread2, . . . , VreadM-1 are applied to the word lines corresponding to a positive activation and the number of passing cells in a bit line is determined for each of these voltages. In a second phase, these M?1 reading voltages are applied to the word lines corresponding to a negative activation and, for each of them, the number of passing cells in the bit line is determined again. The scalar product is then deduced from the difference between the total number of passing cells in the first phase and the total number of passing cells in the second phase.

Abstract: A memory comprising: a resistive-switching element having first and second electrodes separated by a layer of insulator; an energy storage component or load coupled to the resistive-switching element via a first switch; and a control circuit configured: to program the resistive-switching element to have a set state, wherein, in the set state, a filament forms a conducting path between the first and second electrodes; and, following a dissolution of the filament, to recover electrical energy, generated by the dissolution of the filament, from one of the first and second electrodes by activating the first switch.