Abstract: A method for manufacturing an OxRAM type resistive memory cell including a silicon oxide layer, the method including determining manufacturing parameter values enabling the resistive memory cell to have an initial resistance between 107? and 3·109?; and forming on a substrate a stack successively including a first electrode, the silicon oxide layer and a second electrode, by applying the manufacturing parameter values.

Abstract: An OxRAM resistive memory cell includes a lower electrode, an upper electrode, and an active layer which extends between the lower electrode and the upper electrode. The active layer includes a layer of a first electrically insulating oxide, wherein an electrically conductive filament can be formed, then subsequently broken and reformed several times successively. The upper electrode includes a reservoir layer, capable of receiving oxygen, which includes an upper part made of a metal and a lower part made of a second oxide, the second oxide being an oxide of the metal and including a proportion of oxygen such that the second oxide is electrically conductive.

Abstract: A method for determining a value of a manufacturing parameter of a resistive memory cell, the resistive memory cell including a stack of layers, includes providing reference memory cells corresponding to technological alternatives of the stack of layers; measuring for each reference memory cell an initial resistance value; determining for each reference memory cell a programming parameter value selected from among the resistance in a high resistance state and the programming window; establishing a relationship between the programming parameter and the initial resistance from the initial resistance values and the programming parameter values; and determining the manufacturing parameter value for which the programming parameter is greater than or equal to a target value, from the relationship between the programming parameter and the initial resistance and from a dependency relationship between the initial resistance and the manufacturing parameter.

Abstract: A method for resetting an array of RAM cells by applying a sequence of N reset operations, the method including at a first reset operation, defining a first reset technique and performing the first reset operation; at a j-th reset operation of a N?1 subsequent reset operations, j being an integer between 2 and N, if a correction yield of the reset technique used at the (j?1)-th reset operation fulfils a predefined condition, applying the reset technique used at the (j?1)-th reset operation to perform the j-th reset operation, if the correction yield does not fulfil the predefined condition, defining a new reset technique and applying the new reset technique to perform the j-th reset operation, the correction yield being a cumulative correction yield or a relative correction yield, the correction yield for the N reset operations being measured prior to the first reset operation.

Abstract: A method for programming at least one resistive memory cell of an array of resistive memory cells, includes a sequence of N programming cycles, N being an integer greater than or equal to 2, each programming cycle including a set procedure and a reset procedure, each set procedure including the application of a set technique chosen among a plurality of set techniques, the method including acquiring a bit error ratio value corresponding to each programming cycle for each set technique; and at each programming cycle, applying the set technique having the lowest bit error ratio value corresponding to the programming cycle.

Abstract: A memory includes a matrix of resistive memory cells and an interfacing device to interface the matrix, the interfacing device including at least a conversion capacitor, an electric source, a first switch and a second switch, the interfacing device being configured to: a) connect the conversion capacitor to the source by the second switch to charge the conversion capacitor, then, b) disconnect the conversion capacitor from the source and connect the conversion capacitor to the matrix to achieve a conversion between, on the one hand, a resistive state of one of the memory cells of the matrix, and, on the other hand, a state of charge of the conversion capacitor.

Abstract: A method for resetting an array of Resistive Memory cells by applying a sequence of N reset operations, each reset operation including the application of a reset technique, the method including, at the first reset operation, performing the first reset operation by applying the reset technique having the highest relative correction yield; at the j-th reset operation of the N?1 subsequent reset operations, j being an integer number between 2 and N, defining a reset technique to be used at the j-th reset operation and performing the j-th reset operation.

Abstract: A method for calculating a MAC operation is performed by a memory, in particular in the neuromorphic calculation field. It allows performing the scalar product between an activation vector whose elements are binary with a vector of synaptic coefficients, quantised over M>2 levels. The calculation comprises a first phase, in which M?1 reading voltages Vread2, . . . , VreadM-1 are applied to the word lines corresponding to a positive activation and the number of passing cells in a bit line is determined for each of these voltages. In a second phase, these M?1 reading voltages are applied to the word lines corresponding to a negative activation and, for each of them, the number of passing cells in the bit line is determined again. The scalar product is then deduced from the difference between the total number of passing cells in the first phase and the total number of passing cells in the second phase.

Abstract: A memory comprising: a resistive-switching element having first and second electrodes separated by a layer of insulator; an energy storage component or load coupled to the resistive-switching element via a first switch; and a control circuit configured: to program the resistive-switching element to have a set state, wherein, in the set state, a filament forms a conducting path between the first and second electrodes; and, following a dissolution of the filament, to recover electrical energy, generated by the dissolution of the filament, from one of the first and second electrodes by activating the first switch.

Abstract: A selector for a memory cell, intended to change from a resistive state to a conductive state so as to respectively prohibit or authorize access to the memory cell, characterized in that it is made of an alloy consisting of germanium, selenium, arsenic and tellurium.

Abstract: A three dimensional memory includes flat electrodes, each defining a plane; a vertical electrode, extending essentially along an axis perpendicular to the plane defined by each flat electrode; floating electrodes, each situated between a flat electrode and the vertical electrode; first layers of an insulating material, each flat electrode being separated from the preceding and/or following flat electrode by a first layer of an insulating material; first layers of a first active material, each layer of an active material separating a flat electrode from the floating electrode that is associated therewith; a second layer of a second active material separating the vertical electrode from the floating electrodes. The first active material forms a selector or a memory point and the second active material forms a memory point or a selector. Each flat electrode includes first, second and third sub-layers made of, respectively, first, second and third conductive materials.

Abstract: A resistive random access memory device includes a first electrode; a solid electrolyte made of metal oxide extending onto the first electrode; a second electrode able to supply mobile ions circulating in the solid electrolyte made of metal oxide to the first electrode to form a conductive filament between the first and second electrodes when a voltage is applied between the first and second electrodes; an interface layer including a transition metal from groups 3, 4, 5 or 6 of the periodic table and a chalcogen element; the interface layer extending onto the solid electrolyte made of metal oxide, the second electrode extending onto the interface layer.

Abstract: A memory comprising: a resistive-switching element having first and second electrodes separated by a layer of insulator; an energy storage component or load coupled to the resistive-switching element via a first switch; and a control circuit configured: to program the resistive-switching element to have a set state, wherein, in the set state, a filament forms a conducting path between the first and second electrodes; and, following a dissolution of the filament, to recover electrical energy, generated by the dissolution of the filament, from one of the first and second electrodes by activating the first switch.

Abstract: A solution for using elementary electrochemical components, manufactured from the same arrangement of materials and incorporated in a single electronic circuit, for information storage or for energy storage, is presented. Electrochemical components incorporating a first electrode, a second electrode and an active area between the two, can, by the application of different voltages for switching from a highly resistive state to a weakly resistive state or for switching from a state having one given electromotive force to a state having another electromotive force, be used respectively as a memory or as a battery.

Abstract: A method for programming a resistive random access memory including a matrix of memory cells. This method includes a programming procedure that includes applying a programming voltage ramp to the memory cells of a part at least of the matrix, the programming voltage ramp starting at a first non-zero voltage value, called start voltage, and ending at a second voltage value, called stop voltage, greater in absolute value than the first voltage value. The stop voltage is determined such that each memory cell of said at least one part of the matrix has a first probability between 1/(10N) and 1/N of having a programming voltage greater in absolute value than the stop voltage (Vstop), N being the number of memory cells in the at least one part of the matrix.

Abstract: A semiconductor component includes a first electrode, designated flat electrode, defining a plane; a second electrode, designated active electrode, separated from the first electrode by an electrolyte layer; a pillar, designated vertical pillar, extending essentially along an axis perpendicular to the plane defined by the flat electrode, the pillar including a third electrode, designated vertical electrode and an information storage layer, the information storage layer covering a surface of the vertical electrode; the flat electrode and the vertical pillar being laid out so as to form a memory point. In addition, the materials of the active electrode and the electrolyte layer are chosen so as to form an energy storage zone with the flat electrode.

Abstract: A method for managing the endurance of a non-volatile rewritable memory including a dielectric material layer that switches between a high resistance state, with a first resistance value, and a low resistance state, with a second resistance value, the method including at least one of the following operations: at the end of each erasure operation: reading the first resistance value and comparing it with a first predetermined median resistance value, and determining the writing programming conditions from the comparison results; and at the end of each writing operation: reading the second resistance value and comparing it with a second predetermined median resistance value, and determining the erasure programming conditions from the comparison results, linking the programming conditions and the first and second read resistance values, the writing and erasure programming conditions being applied to the electrodes of the stack during the following writing and/or erasure operations.

Abstract: A method for determining a memory window of at least one resistive random access memory cell, the resistive random access memory cell including a high resistance state and a low resistance state, the passage of the resistive random access memory from an initial state among the high resistance state or the low resistance state to another state then the return to the initial state forming a cycle, the method including: measuring the values of the resistances of the high resistance and low resistance states at a given cycle j, j being an integer; determining the memory window to use during the n cycles following the given cycle j, n being an integer, the memory window being calculated by taking into account at least the resistances of the high resistance and low resistance states at the cycle j.

Abstract: A method for managing the endurance of a non-volatile rewritable memory including memory cells each including an ordered stack of a lower electrode, a layer of dielectric material and an upper electrode, the dielectric material switching between a high resistance state and a low resistance state, or vice versa, to enable a writing in the memory cell or an erasure of the memory cell. The method includes at the end of each writing and erasure cycle, reading the erasure conditions of the memory cell in the course of the final erasure operation of the cycle, and comparing the read erasure conditions with a predetermined median erasure value corresponding to a median resistance value which follows a predetermined dependency law linking the condition of erasure of a cycle with the condition of writing of a following cycle; and determining the writing conditions from the results of the comparison.

Abstract: A method for managing the endurance of a non-volatile rewritable memory including memory cells each including an ordered stack of a lower electrode, a layer of dielectric material and an upper electrode, the dielectric material switching between a high resistance state and a low resistance state, or vice versa, to enable a writing in the memory cell or an erasure of the memory cell. The method includes at the end of each writing and erasure cycle, reading the erasure conditions of the memory cell in the course of the final erasure operation of the cycle, and comparing the read erasure conditions with a predetermined median erasure value corresponding to a median resistance value which follows a predetermined dependency law linking the condition of erasure of a cycle with the condition of writing of a following cycle; and determining the writing conditions from the results of the comparison.