Patents by Inventor Gabriel Pares

Gabriel Pares has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220384963
    Abstract: A stack for fabricating an integrated circuit intended to perform an electromagnetic-lens function for a reconfigurable transmitarray antenna, the stack including in succession: a substrate that includes a set of first active components configured to generate a phase shift, and that has first and second opposite surfaces, the first active components being integrated monolithically into the substrate; a metal layer, forming a ground plane on the first surface of the substrate; a layer of a cured polymer, formed on the metal layer; vias that are electrically insulated from the metal layer and that are arranged to electrically connect pairs of planar antennas, each electrically connected pair of planar antennas including first and second planar antennas that are aligned along the normal to the first and second surfaces of the substrate.
    Type: Application
    Filed: May 31, 2022
    Publication date: December 1, 2022
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Gabriel PARES, Antonio CLEMENTE, Bruno REIG
  • Patent number: 11063172
    Abstract: A method is provided for producing a device with light emitting/light receiving diodes, including: producing, on a substrate, a stack including first and second doped semiconductor layers; first etching of the stack, forming first openings through the entire thickness of the second layer; producing dielectric portions covering, in the first openings, the side walls of the second layer; second etching of the stack, extending the first openings until reaching the substrate, delimiting the p-n junctions of the diodes; etching extending the first openings into a part of the substrate; producing first electrically conductive portions in the first openings, forming first electrodes of the diodes, and producing second electrodes electrically connected to the second layer; and eliminating the substrate, forming a collimation grid.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: July 13, 2021
    Assignee: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventor: Gabriel Pares
  • Publication number: 20210043508
    Abstract: A method of manufacturing at least one element crossing a substrate, including a step of electrodeposition of at least a portion of said element in an opening crossing the substrate and on a portion of a conductive seed layer located on said at least a portion of a surface of the substrate, said seed layer portion being located on a same side of the opening as said surface of the substrate.
    Type: Application
    Filed: August 7, 2020
    Publication date: February 11, 2021
    Applicant: Commissariat à l'Énergie Atomique et aux Énergies Alternatives
    Inventor: Gabriel Pares
  • Publication number: 20200194614
    Abstract: Method for producing a device with light emitting/light receiving diodes, comprising: producing, on a substrate, a stack including first and second doped semiconductor layers; first etching of the stack, forming first openings through the entire thickness of the second layer; producing dielectric portions covering, in the first openings, the side walls of the second layer; second etching of the stack, extending the first openings until reaching the substrate, delimiting the p-n junctions of the diodes; etching extending the first openings into a part of the substrate; producing first electrically conductive portions in the first openings, forming first electrodes of the diodes, and producing second electrodes electrically connected to the second layer; eliminating the substrate, forming a collimation grid.
    Type: Application
    Filed: December 6, 2019
    Publication date: June 18, 2020
    Applicant: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventor: Gabriel PARES
  • Patent number: 10629361
    Abstract: An inductance device includes a coil provided with at least one electrically conductive turn having a first portion of turn formed on a face of a first substrate, and a second portion of turn. A first end of the first portion is electrically connected to a first end of the second portion by a conductive connection, and the coil has a longitudinal axis, around which the at least one turn is formed, which is perpendicular to a dimension in thickness of the first substrate. The second portion is formed on a face of a second substrate different from the first substrate, with the face of the first substrate facing the face of the second substrate, with the conductive connection extending into an interstitial space located between the face of the first substrate and the face of the second substrate.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: April 21, 2020
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Jean-Louis Pornin, Gabriel Pares, Bruno Reig
  • Publication number: 20170178791
    Abstract: An inductance device includes a coil provided with at least one electrically conductive turn having a first portion of turn formed on a face of a first substrate, and a second portion of turn. A first end of the first portion is electrically connected to a first end of the second portion by a conductive connection, and the coil has a longitudinal axis, around which the at least one turn is formed, which is perpendicular to a dimension in thickness of the first substrate. The second portion is formed on a face of a second substrate different from the first substrate, with the face of the first substrate facing the face of the second substrate, with the conductive connection extending into an interstitial space located between the face of the first substrate and the face of the second substrate.
    Type: Application
    Filed: December 15, 2016
    Publication date: June 22, 2017
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Jean-Louis PORNIN, Gabriel PARES, Bruno REIG
  • Patent number: 9312169
    Abstract: Method for producing a microelectronic device formed from a stack of supports (W) each provided with one or more electronic components (C) and comprising a conductive structure (170, 470) formed from a first blind conductive via (171b, 472) and a second blind conductive via (171a, 473) with a greater height, the first via and the second via being connected together.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: April 12, 2016
    Assignee: Commissariat a l'energie atomique et aux energies alternatives
    Inventors: Christophe Bouvier, Gabriel Pares
  • Patent number: 9241403
    Abstract: Forming of a microelectronic device including a substrate containing at least one conductive pad, the pad being provided with a bottom surface resting on the substrate and an upper surface opposite the bottom surface. The upper surface of the pad has a stack applied thereto formed of a conductive layer and a protective dielectric layer including an opening called first opening facing the pad and exposing the conductive layer. At least one insulating block is arranged on a peripheral region of the upper surface of the pad, the insulating block having a cross-section forming a closed contour and having an opening called second opening. A conductive pillar is located in the center of the contour in the second opening.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: January 19, 2016
    Assignee: Commissariat à l'énergie atomique et aux énergies alternatives
    Inventor: Gabriel Pares
  • Publication number: 20150044866
    Abstract: Method for producing a microelectronic device formed from a stack of supports (W) each provided with one or more electronic components (C) and comprising a conductive structure (170, 470) formed from a first blind conductive via (171b, 472) and a second blind conductive via (171a, 473) with a greater height, the first via and the second via being connected together.
    Type: Application
    Filed: August 7, 2014
    Publication date: February 12, 2015
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT
    Inventors: Christophe BOUVIER, Gabriel PARES
  • Publication number: 20140144690
    Abstract: The invention concerns the forming of a microelectronic device comprising a substrate containing at least one conductive pad, the said pad being provided with a bottom surface resting on the substrate and an upper surface opposite said bottom surface, the said upper surface of said pad having a stack applied thereto formed of a conductive layer and a protective dielectric layer comprising an opening called first opening facing said pad and exposing the said conductive layer, at least one insulating block (120a, 120b) being arranged on a peripheral region of said upper surface of said pad, the said insulating block (120a, 120b) having a cross-section forming a closed contour and comprising an opening called second opening, a conductive pillar (130a, 130b) being located in the centre of said contour in the said second opening.
    Type: Application
    Filed: November 26, 2013
    Publication date: May 29, 2014
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT
    Inventor: Gabriel Pares
  • Patent number: 8541304
    Abstract: A method for producing an interconnection structure is disclosed. In one aspect, there is formation in a substrate of at least one trench forming a closed contour and at least one hole situated inside the closed contour, the trench and the hole being separated by a zone of the substrate. Furthermore, the trench is filled with a dielectric material and the hole is filled with a conducting material.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: September 24, 2013
    Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventor: Gabriel Pares
  • Publication number: 20110143535
    Abstract: A method for producing an interconnection structure is disclosed. In one aspect, there is formation in a substrate of at least one trench forming a closed contour and at least one hole situated inside the closed contour, the trench and the hole being separated by a zone of the substrate. Furthermore, the trench is filled with a dielectric material and the hole is filled with a conducting material.
    Type: Application
    Filed: December 14, 2010
    Publication date: June 16, 2011
    Applicant: Commissariat a lenergie atomique et aux energies alternatives
    Inventor: Gabriel Pares