Patents by Inventor Gabriel Parmer

Gabriel Parmer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10241911
    Abstract: Examples described herein relate to caching in a system with multiple nodes sharing a globally addressable memory. The globally addressable memory includes multiple windows that each include multiple chunks. Each node of a set of the nodes includes a cache that is associated with one of the windows. One of the nodes includes write access to one of the chunks of the window. The other nodes include read access to the chunk. The node with write access further includes a copy of the chunk in its cache and modifies multiple lines of the chunk copy. After a first line of the chunk copy is modified, a notification is sent to the other nodes that the chunk should be marked dirty. After multiple lines are modified, an invalidation message is sent for each of the modified lines of the set of the nodes.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: March 26, 2019
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Gabriel Parmer, Paolo Faraboschi, Dejan S Milojicic
  • Publication number: 20180060233
    Abstract: Examples described herein relate to caching in a system with multiple nodes sharing a globally addressable memory. The globally addressable memory includes multiple windows that each include multiple chunks. Each node of a set of the nodes includes a cache that is associated with one of the windows. One of the nodes includes write access to one of the chunks of the window. The other nodes include read access to the chunk. The node with write access further includes a copy of the chunk in its cache and modifies multiple lines of the chunk copy. After a first line of the chunk copy is modified, a notification is sent to the other nodes that the chunk should be marked dirty. After multiple lines are modified, an invalidation message is sent for each of the modified lines of the set of the nodes.
    Type: Application
    Filed: August 24, 2016
    Publication date: March 1, 2018
    Inventors: Gabriel Parmer, Paolo Faraboschi, Dejan S. Milojicic
  • Publication number: 20170329526
    Abstract: Example implementations relate to an interoperable capability. For example, in an implementation, an interoperable capability is recognizable by a plurality of kernels of a system, and the interoperable capability references a local capability of respective kernels. Consistency among the local capabilities of the kernels and the interoperable capability is maintained, in response to operations invoked on the interoperable capability.
    Type: Application
    Filed: May 13, 2016
    Publication date: November 16, 2017
    Inventors: Reto Achermann, Maurice Bailleu, Dejan S. Milojicic, Gabriel Parmer