Abstract: Direct bonded stack structures for increased reliability and improved yields in microelectronics are provided. Structural features and stack configurations are provided for memory modules and 3DICs to reduce defects in vertically stacked dies. Example processes alleviate warpage stresses between a thicker top die and direct bonded dies beneath it, for example. An etched surface on the top die may relieve warpage stresses. An example stack may include a compliant layer between dies. Another stack configuration replaces the top die with a layer of molding material to circumvent warpage stresses. An array of cavities on a bonding surface can alleviate stress forces. One or more stress balancing layers may also be created on a side of the top die or between other dies to alleviate or counter warpage. Rounding of edges can prevent stresses and pressure forces from being destructively transmitted through die and substrate layers. These measures may be applied together or in combinations in a single package.

Abstract: A semiconductor element is provided with a micro-structured metal oxide layer over a conductive feature at a hybrid bonding surface. The micro-structured metal oxide layer comprises fine metal oxide grains, such as nanograins. The grains can be formed over the conductive feature by oxidizing a metal comprised in the conductive feature, or by providing a metal oxide over the conductive feature. When directly bonded to another element, the micro-structured metal oxide layer can form strong bonds at the bonding interface at substantially reduced annealing temperature.

Abstract: Embodiments herein are generally directed to ejection assemblies for singulated dies and thinned wafers and methods related thereto. Die ejection assemblies may be used to minimize cracking or deformation of dies during post-singulation processing. Thus, the die ejection assemblies and methods described herein reduce the number of dies rejected after singulation and the number of failures during a die bonding process. In one general aspect, an apparatus for removing singulated dies from a dicing tape is provided. The apparatus may include a die ejector assembly, which may include a vacuum plate configured to engage with a portion of the dicing tape. A die ejector may be disposed in an ejector opening of the vacuum plate. One or more actuators may be configured to move at least a portion of the die ejector in a lateral direction relative to the upper surface of the vacuum plate.

Abstract: A semiconductor element is provided with a micro-structured metal layer over conductive features of a hybrid bonding surface. The micro-structured metal layer comprises fine metal grain microstructure, such as nanograins. The micro-structured metal layer can be formed over the conductive features by providing a metal oxide and reducing the metal oxide to metal. The micro-structured metal layer can be formed selectively if the metal oxide is formed by oxidation. When directly bonded to another element, the micro-structured metal layer forming strong bonds at the bonding interface can substantially reduce annealing temperature.

Abstract: Apparatus and method relating generally to electronics are disclosed. In one such an apparatus, a film assembly has an upper surface and a lower surface opposite the upper surface. A dielectric film of the film assembly has a structured profile along the upper surface or the lower surface for having alternating ridges and grooves in a corrugated section in an at rest state of the film assembly. Conductive traces of the film assembly conform to the upper surface or the lower surface in or on the dielectric film in the corrugated section.

Abstract: In various embodiments, a bonded structure is disclosed. The bonded structure can include an element and a passive electronic component having a first surface bonded to the element and a second surface opposite the first surface. The passive electronic component can comprise a first anode terminal bonded to a corresponding second anode terminal of the element and a first cathode terminal bonded to a corresponding second cathode terminal of the element. The first anode terminal and the first cathode terminal can be disposed on the first surface of the passive electronic component.

Abstract: A method of repairing a bonded structure is disclosed. The method can include debonding from a carrier a first semiconductor element that is bonded to a bonding site of the carrier, cleaning the bonding site of the carrier; and bonding a second semiconductor element to the bonding site of the carrier. The bonding can also include directly bonding the second semiconductor element and the carrier. The method can further include reducing the dielectric bond energy via a surface modification between the first semiconductor element and the carrier. Debonding the bonded structure can include delivering a fluid from one or more nozzles to a bonding interface between the first semiconductor element and the carrier to reduce the bond energy. A temperature adjustment pad can also be included to debond the bonded structure.

Abstract: Direct bonded stack structures for increased reliability and improved yields in microelectronics are provided. Structural features and stack configurations are provided for memory modules and 3DICs to reduce defects in vertically stacked dies. Example processes alleviate warpage stresses between a thicker top die and direct bonded dies beneath it, for example. An etched surface on the top die may relieve warpage stresses. An example stack may include a compliant layer between dies. Another stack configuration replaces the top die with a layer of molding material to circumvent warpage stresses. An array of cavities on a bonding surface can alleviate stress forces. One or more stress balancing layers may also be created on a side of the top die or between other dies to alleviate or counter warpage. Rounding of edges can prevent stresses and pressure forces from being destructively transmitted through die and substrate layers. These measures may be applied together or in combinations in a single package.

Abstract: Direct bonded stack structures for increased reliability and improved yields in microelectronics are provided. Structural features and stack configurations are provided for memory modules and 3DICs to reduce defects in vertically stacked dies. Example processes alleviate warpage stresses between a thicker top die and direct bonded dies beneath it, for example. An etched surface on the top die may relieve warpage stresses. An example stack may include a compliant layer between dies. Another stack configuration replaces the top die with a layer of molding material to circumvent warpage stresses. An array of cavities on a bonding surface can alleviate stress forces. One or more stress balancing layers may also be created on a side of the top die or between other dies to alleviate or counter warpage. Rounding of edges can prevent stresses and pressure forces from being destructively transmitted through die and substrate layers. These measures may be applied together or in combinations in a single package.

Abstract: In various embodiments, a bonded structure is disclosed. The bonded structure can include an element and a passive electronic component having a first surface bonded to the element and a second surface opposite the first surface. The passive electronic component can comprise a first anode terminal bonded to a corresponding second anode terminal of the element and a first cathode terminal bonded to a corresponding second cathode terminal of the element. The first anode terminal and the first cathode terminal can be disposed on the first surface of the passive electronic component.

Abstract: A bonded structure can include a carrier including a first conductive contact and a second conductive contact, a first singulated element including a third conductive contact directly bonded to the first conductive contact without an adhesive, and a second singulated element including a fourth conductive contact directly bonded to the second conductive contact without an adhesive, wherein the first and second conductive contacts are spaced apart by a contact spacing of no more than 250 microns.

Abstract: Disclosed is a stacked electronic device including a first and second bonded structure. The first bonded structure includes a first and second semiconductor element, each having a semiconductor region, a front side on one side of the semiconductor region including active circuitry, and a back side opposite the front side. The front side of the first semiconductor element is bonded and electrically connected to the front side of the second semiconductor element. The second bonded structure includes a third and fourth semiconductor element, which can include similar components to the first and second semiconductor elements. The front side of the third semiconductor element is bonded and electrically connected to the front side of the fourth semiconductor element. The back side of the second semiconductor element is bonded and electrically connected to the back side of the third semiconductor element.

Abstract: Methods of bonding thin dies to substrates. In one such method, a wafer is attached to a support layer. The wafer and support layer are attached to a dicing structure and then singulated to form a plurality of semiconductor die components. Each semiconductor die component comprises a thinned die and a support layer section attached to the thinned die where each support layer section is disposed between the corresponding thinned die and the dicing structure. At least one of the semiconductor die components is then bonded to a substrate without an intervening adhesive such that the thinned die is disposed between the substrate and the support layer section. The support layer section is then removed from the thinned die.

Abstract: In various embodiments, a bonded structure is disclosed. The bonded structure can include an element and a passive electronic component having a first surface bonded to the element and a second surface opposite the first surface. The passive electronic component can comprise a first anode terminal bonded to a corresponding second anode terminal of the element and a first cathode terminal bonded to a corresponding second cathode terminal of the element. The first anode terminal and the first cathode terminal can be disposed on the first surface of the passive electronic component.

Abstract: Direct bonded stack structures for increased reliability and improved yields in microelectronics are provided. Structural features and stack configurations are provided for memory modules and 3DICs to reduce defects in vertically stacked dies. Example processes alleviate warpage stresses between a thicker top die and direct bonded dies beneath it, for example. An etched surface on the top die may relieve warpage stresses. An example stack may include a compliant layer between dies. Another stack configuration replaces the top die with a layer of molding material to circumvent warpage stresses. An array of cavities on a bonding surface can alleviate stress forces. One or more stress balancing layers may also be created on a side of the top die or between other dies to alleviate or counter warpage. Rounding of edges can prevent stresses and pressure forces from being destructively transmitted through die and substrate layers. These measures may be applied together or in combinations in a single package.

Abstract: Direct bonded stack structures for increased reliability and improved yields in microelectronics are provided. Structural features and stack configurations are provided for memory modules and 3DICs to reduce defects in vertically stacked dies. Example processes alleviate warpage stresses between a thicker top die and direct bonded dies beneath it, for example. An etched surface on the top die may relieve warpage stresses. An example stack may include a compliant layer between dies. Another stack configuration replaces the top die with a layer of molding material to circumvent warpage stresses. An array of cavities on a bonding surface can alleviate stress forces. One or more stress balancing layers may also be created on a side of the top die or between other dies to alleviate or counter warpage. Rounding of edges can prevent stresses and pressure forces from being destructively transmitted through die and substrate layers. These measures may be applied together or in combinations in a single package.

Abstract: Configurable smart object systems with methods of making modules and contactors are provided. Example systems implement machine learning based on neural networks that draw low power for use in smart phones, watches, drones, automobiles, and medical devices. Example assemblies can be configured from pluggable, interchangeable modules that have compatible ports for interconnecting and integrating functionally dissimilar sensor systems. An example method includes mounting an element of a configurable machine learning assembly on a substrate, creating at least one fold in the substrate, folding the substrate at the fold into a housing of a module of the configurable machine learning assembly, and adding a molding material to the housing to at least partially fill the module of the configurable machine learning assembly. The example module construction may also form contactors on folded edges of the module for making physical and electrical contact with other modules of the smart object machine learning assembly.

Abstract: Configurable smart object systems with grid or frame-based connectors are provided. Example systems implement machine learning based on neural networks that draw low power for use in smart phones, watches, drones, automobiles, and medical devices, for example. Example assemblies can be configured from pluggable, interchangeable modules that have compatible ports with magnetic electrical contacts for interconnecting and integrating functionally dissimilar sensor systems. An example system has a clip attachable to a substrate for securing a smart object module to the substrate, and a housing of the clip with a geometry for aligning electrical contacts of the smart object module with electrical contacts of the substrate. The clip may have a compliant layer to provide spring, resilience, or pressure to securing the smart object module to the substrate. The clip may also integrate features of a secure digital (SD) port and a universal serial bus (USB) port.

Abstract: Apparatus and method relating generally to electronics are disclosed. In one such an apparatus, a film assembly has an upper surface and a lower surface opposite the upper surface. A dielectric film of the film assembly has a structured profile along the upper surface or the lower surface for having alternating ridges and grooves in a corrugated section in an at rest state of the film assembly. Conductive traces of the film assembly conform to the upper surface or the lower surface in or on the dielectric film in the corrugated section.

Abstract: Apparatus and method relating generally to electronics are disclosed. In one such an apparatus, a film assembly has an upper surface and a lower surface opposite the upper surface. A dielectric film of the film assembly has a structured profile along the upper surface or the lower surface for having alternating ridges and grooves in a corrugated section in an at rest state of the film assembly. Conductive traces of the film assembly conform to the upper surface or the lower surface in or on the dielectric film in the corrugated section.