Abstract: The invention relates to a semiconductor component comprising a semiconductor body, an insulation on the semiconductor body and a cell array arranged at least partly within the semiconductor body. The cell array has at least one p-n junction and at least one contact connection. The insulation is bounded in lateral direction of the semiconductor body by a circumferential diffusion barrier.

Abstract: The invention relates to a semiconductor component comprising a semiconductor body, an insulation on the semiconductor body and a cell array arranged at least partly within the semiconductor body. The cell array has at least one p-n junction and at least one contact connection. The insulation is bounded in lateral direction of the semiconductor body by a circumferential diffusion barrier.

Abstract: The invention relates to a semiconductor circuit arrangement having a semiconductor substrate, a first doping region, a second doping region, a connection doping region, an insulation layer and an electrically conductive structure which is to be planarized, it being possible for the charge carriers formed during a planarization step to be reliably dissipated, and for dendrite formation to be prevented, by a discharge doping region formed in the first and second doping regions.

Abstract: The invention relates to a semiconductor circuit arrangement having a semiconductor substrate, a first doping region, a second doping region, a connection doping region, an insulation layer and an electrically conductive structure which is to be planarized, it being possible for the charge carriers formed during a planarization step to be reliably dissipated, and for dendrite formation to be prevented, by a discharge doping region formed in the first and second doping regions.

Abstract: The invention relates to a semiconductor circuit arrangement having a semiconductor substrate, a first doping region, a second doping region, a connection doping region, an insulation layer and an electrically conductive structure which is to be planarized, it being possible for the charge carriers formed during a planarization step to be reliably dissipated, and for dendrite formation to be prevented, by a discharge doping region formed in the first and second doping regions.

Abstract: The novel etching process for a two-layer metallization, or dual damascene patterning, is simple and cost-effective to carry out and reliably prevents fences from forming during the etching process in the region of the polymer intermediate layer. The etching of the oxide layer and of the polymer intermediate layer for the dual damascene patterning is effected by a CF4 ARC open process with high selectivity with respect to the photoresist with a lengthened etching time.

Abstract: A method for forming a dual damascene structure for a semiconductor device, in accordance with the present invention, includes providing conductive regions on a first layer, forming an interlevel dielectric layer over the first layer and forming an etch stop layer over the interlevel dielectric layer. The etch stop layer includes a polymer material having a dielectric constant of less than about 3.0. The etch stop layer is patterned to form a via pattern, and a trench dielectric layer is deposited on the etch stop layer and in holes of the via pattern. Trenches are formed in the trench dielectric layer by etching the trench layer in accordance with a trench pattern, and vias are formed in the interlevel dielectric layer by etching through the trenches using the etch stop layer to self-align the trenches to the vias and expose the conductive regions on the first layer.

Abstract: An interconnection pattern is formed over the surface of a silicon wafer in which both the vias and the trenches of the pattern are filled with copper. The process of filling the vias and trenches involves use of a silicon nitride film as an etch stop and the filling of the vias with an anti-reflection coating.

Abstract: A method is provided for forming a step in a layer of material. The method includes forming the layer over a substrate. A cavity is formed in a portion of an upper surface of the layer. The formed cavity is filled with a filler material to provide a substantially planar surface over the substrate. A photoresist layer is formed over the substantially planar surface over the substrate. An aperture is formed in the photoresist layer in registration with the formed cavity. The aperture exposes a portion of the filler material. The exposed portion of the filler material is removed along with a contiguous portion of the layer to form the step in the indentation. The cavity may be either a trench or a via. A “Trench First” approach and a “Via First” approach are described.

Abstract: A MIM capacitor (52) comprising a bottom plate (26), a capacitor dielectric (30) and a top plate (46). The capacitor bottom plate (26) is formed within an insulating layer (20) for a contact via (32) layer. The capacitor top plate (46) is formed within an insulating layer (34) of a metallization layer. The MIM capacitor (52) may be fabricated without the use of additional processes and patterning masks.

Abstract: The novel etching process for a two-layer metallization, or dual damascene patterning, is simple and cost-effective to carry out and reliably prevents fences from forming during the etching process in the region of the polymer intermediate layer. The etching of the oxide layer and of the polymer intermediate layer for the dual damascene patterning is effected by a CF4 ARC open process with high selectivity with respect to the photoresist with a lengthened etching time.