Abstract: One illustrative method disclosed herein includes performing an atomic layer deposition (ALD) process at a temperature of less than 400° C. to deposit a layer of silicon dioxide on a germanium-containing region of semiconductor material and forming a gate structure of a transistor device above the layer of silicon dioxide.

Abstract: Methods for fabricating integrated circuits and components thereof are provided. In accordance with an exemplary embodiment, a method for fabricating an integrated circuit is provided. The method includes providing a semiconductor substrate with a first gate structure and a second gate structure and a shallow trench isolation region outside of the first and second gate structures, depositing a mask on the first gate structure, and depositing a protection layer on the shallow trench isolation region to embed a STI protective cap.

Abstract: Semiconductor device structures at advanced technologies are provided, wherein a reliable encapsulation of a gate dielectric is already formed during very early stages of fabrication. In illustrative embodiments, a gate stack is formed over a surface of a semiconductor substrate and a sidewall spacer is formed adjacent to the gate stack for covering sidewall surfaces of the gate stack. An additional thin layer is formed over the sidewall spacer, the gate stack and the surface of the semiconductor substrate, and thereafter source/drain extension regions are implanted through the additional thin layer into the substrate in alignment with the sidewall spacer.

Abstract: In sophisticated semiconductor devices, transistors may be formed on the basis of an efficient strain-inducing mechanism by using an embedded strain-inducing semiconductor alloy. The strain-inducing semiconductor material may be provided as a graded material with a smooth strain transfer into the neighboring channel region in order to reduce the number of lattice defects and provide enhanced strain conditions, which in turn directly translate into superior transistor performance. The superior architecture of the graded strain-inducing semiconductor material may be accomplished by selecting appropriate process parameters during the selective epitaxial growth process without contributing to additional process complexity.

Abstract: One illustrative method disclosed herein includes performing an atomic layer deposition (ALD) process at a temperature of less than 400° C. to deposit a layer of silicon dioxide on a germanium-containing region of semiconductor material and forming a gate structure of a transistor device above the layer of silicon dioxide.

Abstract: In sophisticated semiconductor devices, transistors may be formed on the basis of an efficient strain-inducing mechanism by using an embedded strain-inducing semiconductor alloy. The strain-inducing semiconductor material may be provided as a graded material with a smooth strain transfer into the neighboring channel region in order to reduce the number of lattice defects and provide enhanced strain conditions, which in turn directly translate into superior transistor performance. The superior architecture of the graded strain-inducing semiconductor material may be accomplished by selecting appropriate process parameters during the selective epitaxial growth process without contributing to additional process complexity.